Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE Vehicular Technology Conference (VTC)en_US
dc.citation.locationDallas, TXen_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.authorMcCain, Dennisen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:46:24Zen_US
dc.date.available2007-10-31T00:46:24Zen_US
dc.date.issued2005-09-01en_US
dc.date.modified2005-06-25en_US
dc.date.note2005-06-24en_US
dc.date.submitted2005-09-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractIn this paper, we propose a parallel and pipelined VLSI architecture for a circulant approximated equalizer for the MIMOCDMA systems. The FFT-based tap solver reduces the Direct-Matrix-Inverse of the size (NF x NF) to the inverse of O(N) sub-matrices of the size (N x N). Hermitian optimization and tree pruning is proposed to reduce the number and complexity of the FFTs. A divide-andconquer method partitions the 4£4 sub-matrices into 2x2 sub-matrices and simplifies the inverse of sub-matrices. Generic VLSI architecture is derived to eliminate the redundancies in the complex operations. Multiple level parallelism and pipelining is investigated with a Catapult C High-Level-Synthesis (HLS) methodology. This leads to efficient VLSI architectures with 3x further complexity reduction. The scalable VLSI architectures are prototyped with the Xilinx FPGAs and achieve area/time efficiency.en_US
dc.identifier.citationY. Guo, D. McCain and J. R. Cavallaro, "Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink," 2005.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/VETECF.2005.1558489en_US
dc.identifier.urihttps://hdl.handle.net/1911/19940en_US
dc.language.isoengen_US
dc.subjectMIMOen_US
dc.subjectCDMAen_US
dc.subjectchip equalizeren_US
dc.subjectHermitian optimizationen_US
dc.subject.keywordMIMOen_US
dc.subject.keywordCDMAen_US
dc.subject.keywordchip equalizeren_US
dc.subject.keywordHermitian optimizationen_US
dc.titleHermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlinken_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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