The Vandermonde system is used in OFDM predistortion to enhance the power efficiency dramatically. In this paper, we study efficient FPGA architectures of a recursive algorithm for the Cholesky and QR factorization of the Vandermonde system. We identify the key bottlenecks of the algorithm for the real-time constraints and resource consumption. Several architecture/resource tradeoffs are studied to find the commonalities in the architectures for a best partitioning. Hardware resources are reused according to the algorithmic parallelism and data dependency to achieve the best timing/area performance in hardware. The architectures are implemented in Xilinx FPGA and tested in Aptix real-time hardware platform with 11348 cycles at 25ns clock rate.