A reconfigurable decoder architecture for wireless LAN and cellular systems
| dc.contributor.advisor | Cavallaro, Joseph R. | en_US |
| dc.creator | Chadha, Kanu | en_US |
| dc.date.accessioned | 2009-06-04T06:44:35Z | en_US |
| dc.date.available | 2009-06-04T06:44:35Z | en_US |
| dc.date.issued | 2001 | en_US |
| dc.description.abstract | The rapid growth of wireless communications has led to the demand for communication devices which can support multiple standards and have the capability of switching from one to another on-the-fly. For instance, a device which could support the Wireless Local Area Network (LAN) and Wideband Code Division Multiple Access (WCDMA) standards would enable seamless communications in the indoor LAN network as well as the outdoor cellular environment. A key challenge involved in the building of such a communications device is the design of a flexible hardware architecture that can dynamically reconfigure itself to run different algorithms as required to support the different standards. In particular, the Viterbi decoding algorithm is used at the receiver of both WCDMA and WLAN systems to decode the convolutionally encoded data. The difference lies in the encoding parameters such as the constraint length, code rate and generator polynomials. In this thesis, we propose an architecture for a reconfigurable Viterbi decoder that can dynamically adapt to changes in the encoding parameters. The proposed architecture is implemented on a Field Programmable Gate Array (FPGA) device. The proposed architecture can be used to realize a Viterbi decoder which can support constraint lengths from 3 to 9 and rates 1/2 and 1/3. | en_US |
| dc.format.extent | 66 p. | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.callno | THESIS E.E. 2001 CHADHA | en_US |
| dc.identifier.citation | Chadha, Kanu. "A reconfigurable decoder architecture for wireless LAN and cellular systems." (2001) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/17406">https://hdl.handle.net/1911/17406</a>. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/17406 | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | en_US |
| dc.subject | Electronics | en_US |
| dc.subject | Electrical engineering | en_US |
| dc.title | A reconfigurable decoder architecture for wireless LAN and cellular systems | en_US |
| dc.type | Thesis | en_US |
| dc.type.material | Text | en_US |
| thesis.degree.department | Electrical Engineering | en_US |
| thesis.degree.discipline | Engineering | en_US |
| thesis.degree.grantor | Rice University | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science | en_US |
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