Automated Deep Learning Algorithm and Accelerator Co-search for Both Boosted Hardware Efficiency and Task Accuracy
| dc.contributor.advisor | Lin, Yingyan | en_US |
| dc.creator | Zhang, Yongan | en_US |
| dc.date.accessioned | 2023-05-31T20:30:19Z | en_US |
| dc.date.available | 2023-05-31T20:30:19Z | en_US |
| dc.date.created | 2023-08 | en_US |
| dc.date.issued | 2023-04-24 | en_US |
| dc.date.submitted | August 2023 | en_US |
| dc.date.updated | 2023-05-31T20:30:19Z | en_US |
| dc.description.abstract | Powerful yet complex deep neural networks (DNNs) have fueled a booming demand for efficient DNN solutions to bring DNN-powered intelligence into numerous applications. Jointly optimizing the networks and their accelerators are promising in providing optimal performance. However, the great potential of such solutions have yet to be unleashed due to the challenge of simultaneously exploring the vast and entangled, yet different design spaces of the networks and their accelerators. To this end, we propose DIAN, a DIfferentiable Accelerator-Network co-search framework for automatically searching for matched networks and accelerators to maximize both the task accuracy and acceleration efficiency. Specifically, DIAN integrates two enablers: (1) a generic design space for DNN accelerators that is applicable to both FPGA- and ASIC-based DNN accelerators and compatible with DNN frameworks such as PyTorch to enable algorithmic exploration for more efficient DNNs and their accelerators; and (2) a joint DNN network and accelerator co-search algorithm that enables the simultaneous search for optimal DNN structures and their accelerators’ micro-architectures and mapping methods to maximize both the task accuracy and acceleration efficiency. Experiments and ablation studies based on FPGA measurements and ASIC synthesis show that the matched networks and accelerators generated by DIAN consistently outperform state-of-the-art (SOTA) DNNs and DNN accelerators (e.g., 3.04× better FPS with a 5.46% higher accuracy on ImageNet), while requiring notably reduced search time (up to 1234.3×) over SOTA co-exploration methods, when evaluated over ten SOTA baselines on three datasets. | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.citation | Zhang, Yongan. "Automated Deep Learning Algorithm and Accelerator Co-search for Both Boosted Hardware Efficiency and Task Accuracy." (2023) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/114896">https://hdl.handle.net/1911/114896</a>. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/114896 | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | en_US |
| dc.subject | Deep Learning | en_US |
| dc.subject | Hardware Acceleration | en_US |
| dc.subject | Hardware Design Automation | en_US |
| dc.subject | Algorithm-Hardware Co-design | en_US |
| dc.title | Automated Deep Learning Algorithm and Accelerator Co-search for Both Boosted Hardware Efficiency and Task Accuracy | en_US |
| dc.type | Thesis | en_US |
| dc.type.material | Text | en_US |
| thesis.degree.department | Electrical and Computer Engineering | en_US |
| thesis.degree.discipline | Engineering | en_US |
| thesis.degree.grantor | Rice University | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science | en_US |
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