Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameInternational Symposium on High Performance Computer Architecture (HPCA)en_US
dc.citation.firstpage23
dc.citation.lastpage32
dc.citation.locationOrlando, FLen_US
dc.contributor.authorDurbhakula, Murthyen_US
dc.contributor.authorPai, Vijay S.en_US
dc.contributor.authorAdve, Sarita V.en_US
dc.contributor.orgCITI (http://citi.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:43:13Z
dc.date.available2007-10-31T00:43:13Z
dc.date.issued1999-01-20
dc.date.modified2002-03-20en_US
dc.date.note2002-03-20en_US
dc.date.submitted1999-01-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractNoneen_US
dc.identifier.citationM. Durbhakula, V. S. Pai and S. V. Adve, "Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors," 1999.
dc.identifier.urihttps://hdl.handle.net/1911/19868
dc.language.isoeng
dc.subjectperformance evaluation*
dc.subjectshared-memory multiprocessors*
dc.subjectinstruction-level parallelism*
dc.subjectmemory parallelism*
dc.subject.keywordperformance evaluationen_US
dc.subject.keywordshared-memory multiprocessorsen_US
dc.subject.keywordinstruction-level parallelismen_US
dc.subject.keywordmemory parallelismen_US
dc.titleImproving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processorsen_US
dc.typeConference paper
dc.type.dcmiText
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