CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameUniversity/Government/Industry Microelectronics Symposiumen_US
dc.citation.firstpage64en_US
dc.citation.lastpage69en_US
dc.citation.locationMelbourne, FLen_US
dc.contributor.authorHemkumar, Nariankadu D.en_US
dc.contributor.authorKota, Kishoreen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:46:34Zen_US
dc.date.available2007-10-31T00:46:34Zen_US
dc.date.issued1991-06-20en_US
dc.date.modified2001-08-28en_US
dc.date.note2001-08-28en_US
dc.date.submitted1991-06-20en_US
dc.descriptionConference paperen_US
dc.description.abstractThe SVD is an important matrix decomposition in many real-time signal processing, image processing and robotics applications. Special-purpose processor arrays can achieve significant speed-up over conventioinal architectures through the use of efficient parallel algorithms. The Cordic Array Processor Element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix. The array utilizes CORDIC (Co-ordinate Rotation Digital Computer) arithmetic to perform the vector rotations and inverse tangent calculations in hardware. A six-chip prototype of the processor has been implemented as TinyChips using the MOSIS fabricatioin service. Experience gained from designing the prototype helped in the design of integrated single chip version. The chip has been implemented on a 5600 x 6900ì die in a 2ì n-well scalable CMOS process.en_US
dc.identifier.citationN. D. Hemkumar, K. Kota and J. R. Cavallaro, "CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing," 1991.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/UGIM.1991.148123en_US
dc.identifier.urihttps://hdl.handle.net/1911/19944en_US
dc.language.isoengen_US
dc.subjectCordic Array Processor Element (CAPE)en_US
dc.subjectVLSI implementationen_US
dc.subjectsystolic processor arrayen_US
dc.subjectCORDIC (Co-ordinate Rotation Digital Computer)en_US
dc.subjectSVDen_US
dc.subjectmatrixen_US
dc.subject.keywordCordic Array Processor Element (CAPE)en_US
dc.subject.keywordVLSI implementationen_US
dc.subject.keywordsystolic processor arrayen_US
dc.subject.keywordCORDIC (Co-ordinate Rotation Digital Computer)en_US
dc.subject.keywordSVDen_US
dc.subject.keywordmatrixen_US
dc.titleCAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testingen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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