Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)en_US
dc.citation.firstpage251
dc.citation.lastpage261
dc.citation.locationThe Hague, The Netherlandsen_US
dc.contributor.authorChandrasekhar, Vikramen_US
dc.contributor.authorLivingston, Franken_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:38:47Z
dc.date.available2007-10-31T00:38:47Z
dc.date.issued2003-06-20
dc.date.modified2003-11-09en_US
dc.date.note2003-08-07en_US
dc.date.submitted2003-06-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractReduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems specified by standards such as the UMTS, IMT2000. This paper explores the architectural design-space and methodologies for reducing the dynamic power dissipation in the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink RAKE receiver. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving significant power reduction, while highlighting the corresponding performance trade-offs. At the algorithm level, we investigate the tradeoffs of reduced precision and arithmetic complexity on the receiver performance. We then present two architectures for implementing the reference and reduced complexity receivers, and analyze these architectures with respect to their dynamic power dissipation. Our findings report that reduction in precision from a 16 bit to a 10 bit data-path is found to yield significant power savings of 25.6% in the reference RAKE receiver architecture, with a performance loss of less than 1 dB. Further, a power reduction of upto 24.65% is achieved in a 16 bit data-path for the reduced complexity RAKE receiver compared to the reference architecture, with a performance loss of less than 2 dB. Although there is a tradeoff in performance, adaptive power saving is very important for mobile wireless terminals. The combined effect of reduced precision and complexity reduction leads to a 37.44% savings in baseband processing power.en_US
dc.description.sponsorshipNokiaen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationV. Chandrasekhar, F. Livingston and J. R. Cavallaro, "Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers," 2003.
dc.identifier.doihttp://dx.doi.org/10.1109/ASAP.2003.1212850en_US
dc.identifier.urihttps://hdl.handle.net/1911/19769
dc.language.isoeng
dc.subjectLow-Power*
dc.subjectRake Receiver*
dc.subjectFPGA Implementation*
dc.subjectFixed-Point Arithmetic*
dc.subject.keywordLow-Poweren_US
dc.subject.keywordRake Receiveren_US
dc.subject.keywordFPGA Implementationen_US
dc.subject.keywordFixed-Point Arithmeticen_US
dc.titleReducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receiversen_US
dc.typeConference paper
dc.type.dcmiText
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