In this paper, we propose an un-timed C/C++ level verification methodology that integrates key technologies for truly high-level VLSI modelling to keep pace with the explosive complexity of SoC designs in the 3G and beyond wireless communications. A Catapult C/C++ based architecture scheduler transfers the major workload to the algorithmic C/C++ fixed-point design. Case study is given to explore the VLSI design space extensively for various types of computational intensive algorithms in MIMO-CDMA systems, such as a MIMO equalizer to avoid the Direct-Matrix-Inverse. Extensive time/area tradeoff study is enabled with different architecture and resource constraints in a short design cycle. Architecture efficiency and productivity are improved significantly, enabling truly rapid prototyping for the 3G and beyond wireless systems.