High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameEuropean Signal Processing Conferenceen_US
dc.contributor.authorRadosavljevic, Predragen_US
dc.contributor.authorde Baynast, Alexandreen_US
dc.contributor.authorKarkooti, Marjanen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:58:26Zen_US
dc.date.available2007-10-31T00:58:26Zen_US
dc.date.issued2006-02-01en_US
dc.date.modified2006-03-08en_US
dc.date.note2006-03-08en_US
dc.date.submitted2006-02-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractHigh throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for pre-determined set of code rates. Designed decoder achieves data throughput of approximately 1 Gb/s without sacrificing error-correcting performance of capacity-approaching irregular block codes. The prototype architecture is implemented on FPGA.en_US
dc.identifier.citationP. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro, "High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices," 2006.en_US
dc.identifier.urihttps://hdl.handle.net/1911/20209en_US
dc.language.isoengen_US
dc.subjectBlock-structured LDPC codesen_US
dc.subjectlayered belief propgationen_US
dc.subjectarchitecture-oriented design of parity-check matricesen_US
dc.subjectflexible high-throughput architectureen_US
dc.subjectpipelining of horizontal layersen_US
dc.subjectFPGA implementationen_US
dc.subject.keywordBlock-structured LDPC codesen_US
dc.subject.keywordlayered belief propgationen_US
dc.subject.keywordarchitecture-oriented design of parity-check matricesen_US
dc.subject.keywordflexible high-throughput architectureen_US
dc.subject.keywordpipelining of horizontal layersen_US
dc.subject.keywordFPGA implementationen_US
dc.titleHigh-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matricesen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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