A bit-streaming pipelined multiuser detector for wireless communications
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | IEEE International Symposium on Circuits and Systems (ISCAS) | en_US |
| dc.citation.firstpage | 128 | |
| dc.citation.lastpage | 131 | |
| dc.citation.location | Sydney, Australia | en_US |
| dc.citation.volumeNumber | IV | en_US |
| dc.contributor.author | Rajagopal, Sridhar | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:59:02Z | |
| dc.date.available | 2007-10-31T00:59:02Z | |
| dc.date.issued | 2001-05-20 | |
| dc.date.modified | 2003-11-10 | en_US |
| dc.date.note | 2001-09-20 | en_US |
| dc.date.submitted | 2001-05-20 | en_US |
| dc.description | Conference paper | en_US |
| dc.description.abstract | This paper presents a bit-streaming, pipelined and reduced complexity architecture to meet real-time requirements for asynchronous multiuser detection in wireless communication CDMA receivers. Typically, asynchronous multiuser detection involves multishot detection, which involves block-based computations and matrix inversions. Hence, iterative based suboptimal schemes have been studied to decrease the computational complexity and eliminate the need for matrix inversions. However, we show that such low-complexity schemes can have an added advantage of avoiding multishot detection if they start from a matched filter estimate. The stages of the iteration can be pipelined and bits processed in a streaming fashion. We show that such an implementation scheme reduces the latency of the bits by the detection window length <i>D</i> and eliminates the storage requirements for block computation, which helps in DSP implementations. We also avoid edge-bit computation effects, which reduces the computation by 2/<i>D</i> per detection stage. This scheme also results in a simple, bit-streaming and pipelined architecture. DSP simulations show that data rates of 800 Kbps for a single user to 50 Kbps for 32 users can be processed in real-time with additional FPGAs in a pipelined fashion for a spreading gain of 31, giving at least a 4X speedup over a single DSP implementation. | en_US |
| dc.description.sponsorship | Texas Advanced Technology Program | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | S. Rajagopal and J. R. Cavallaro, "A bit-streaming pipelined multiuser detector for wireless communications," vol. IV, 2001. | |
| dc.identifier.doi | http://dx.doi.org/10.1109/ISCAS.2001.922187 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20222 | |
| dc.language.iso | eng | |
| dc.subject | CDMA receivers | * |
| dc.subject | bit-streaming | * |
| dc.subject | multiuser detector | * |
| dc.subject | multishot | * |
| dc.subject.keyword | CDMA receivers | en_US |
| dc.subject.keyword | bit-streaming | en_US |
| dc.subject.keyword | multiuser detector | en_US |
| dc.subject.keyword | multishot | en_US |
| dc.title | A bit-streaming pipelined multiuser detector for wireless communications | en_US |
| dc.type | Conference paper | |
| dc.type.dcmi | Text |