Frequency synthesizers are among the major building blocks of most Radio Frequency (RF) wireless and wireline transceivers as well as digital processors. Its applications range from providing the LO signal for frequency down-conversion in receivers (Rx) and frequency up-conversion in transmitters (Tx), to generating the Clock signal in CPUs. Traditionally, different types of Phase-Locked Loops (PLL) and Delay-Locked Loops (DLL) serve as the synthesizer in such systems. However, they usually suffer from low settling time and high phase noise - or high jitter - which limit their full deployment in stringent standards.

In this work, we propose a new architecture for frequency multiplication based on signal regeneration in a loop and injection locking. Unlike PLL and DLL, this structure benefits from (i) generating the RF signal directly from the input without any voltage to phase/delay conversion and hence having a better phase noise (PN), (ii) no need of precisely matched charge-pumps, (iii) eliminating the off-chip passive components of the low-pass filter (LPF) after Phase Detector (PD) / Phase Frequency Detector (PFD) in the PLL, (iv) eliminating bandwidth/phase noise/stability/settling time constraints, hence being able to operate with very low reference frequency.

This thesis presents the first regenerative multiplier implemented in 65-nm CMOS technology that multiplies a 1 GHz by 4 and enjoys the very low phase noise of -116 dBc/Hz and -138 dBc/Hz at 1 KHz and 1 MHz offsets respectively. Also, a 6.6-9.4 GHz integer-N frequency synthesizer has been designed and simulated. Novel system and circuit level ideas have been deployed to lower the PN as well as the spur level of the output spectrum. By optimizing the design in terms of power and area, this new architecture can be the next generation of RF frequency synthesizers that can enable defining the next generation of communication standards.