A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems

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dc.citation.bibtexNamearticleen_US
dc.citation.journalTitleJournal of VLSI Signal Processingen_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:46:15Z
dc.date.available2007-10-31T00:46:15Z
dc.date.issued2005-05-01
dc.date.modified2006-02-06en_US
dc.date.submitted2006-02-06en_US
dc.descriptionJournal Paperen_US
dc.description.abstractIn this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from O(K^2N) to O(KN). The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least 10X saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least 4£ speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to 90%.en_US
dc.identifier.citationY. Guo and J. R. Cavallaro, "A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems," <i>Journal of VLSI Signal Processing,</i> 2005.
dc.identifier.doihttp://dx.doi.org/10.1007/s11265-006-8535-9en_US
dc.identifier.urihttps://hdl.handle.net/1911/19936
dc.language.isoeng
dc.subjectInterference cancellation*
dc.subjectlow power*
dc.subjectCDMA*
dc.subjectadaptive*
dc.subjectSoC*
dc.subjectVLSI.*
dc.subject.keywordInterference cancellationen_US
dc.subject.keywordlow poweren_US
dc.subject.keywordCDMAen_US
dc.subject.keywordadaptiveen_US
dc.subject.keywordSoCen_US
dc.subject.keywordVLSI.en_US
dc.titleA low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systemsen_US
dc.typeJournal article
dc.type.dcmiText
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