Fault detection in linear sequential circuits
| dc.contributor.advisor | Jump, J. Robert | |
| dc.creator | Petrovic, Aleksa Sime | |
| dc.date.accessioned | 2016-04-22T21:58:11Z | |
| dc.date.available | 2016-04-22T21:58:11Z | |
| dc.date.issued | 1969 | |
| dc.description.abstract | This thesis is concerned with the detection of non-transient faults in digital networks. A procedure for detection of faults in a simple controllable Linear Sequential Circuit (LSC) over GF(2) is developed. The following is assumed: 1) The faults are those which cause the LSC to behave as if some of its primary (external) or secondary (internal) terminals were permanently stuck at zero, or permanently stuck at one; 2) That all testing must be performed on the external terminals of the LSC. The characterizing matrix B, s vectors of the form AnBdv (v=l,2,...,s), s unit input vectors and the zero input vector are used instead of the fault table. (s is the number of primary input terminals, n is the dimension of LSC, A is its characteristic matrix and Sv is the unit input vector having 1 on the position v.) It is shown that the set of s+1 tests is sufficient to detect the existence of any fault that belongs to the set of defined faults. The test is defined here as a procedure consisting of: (a) Application of the unit input vector (or zero input vector) followed by 2n zero input vectors, (b) Comparison of the resulting output vectors with the vectors AnBdv. There are no faults in the LSC if and only if these vectors agree. It is further shown that for an arbitrary LSC over GF(2) realized in pseudo-canonical realization of m simple controllable LSCs, the set of (s+l).m tests is sufficient (m is the number of primary output terminals). | |
| dc.format.digitalOrigin | reformatted digital | en_US |
| dc.format.extent | 75 pp | en_US |
| dc.identifier.callno | Thesis E.E. 1969 PETROVIC | en_US |
| dc.identifier.citation | Petrovic, Aleksa Sime. "Fault detection in linear sequential circuits." (1969) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/89699">https://hdl.handle.net/1911/89699</a>. | |
| dc.identifier.digital | RICE0730 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/89699 | |
| dc.language.iso | eng | |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | |
| dc.title | Fault detection in linear sequential circuits | |
| dc.type | Thesis | |
| dc.type.material | Text | |
| thesis.degree.department | Electrical Engineering | |
| thesis.degree.discipline | Engineering | |
| thesis.degree.grantor | Rice University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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