Performance prediction of packet switched multistage interconnection networks in an execution-driven environment
| dc.contributor.advisor | Jump, J. Robert | |
| dc.creator | Lauderdale, Grant Matthew | |
| dc.date.accessioned | 2009-06-03T23:58:53Z | |
| dc.date.available | 2009-06-03T23:58:53Z | |
| dc.date.issued | 1990 | |
| dc.description.abstract | This thesis studies the performance of multistage interconnection networks (MINs) using execution-driven simulation. The networks were studied with varying network configurations, numbers of inputs and outputs of the network switches, sizes of the switch buffers, switch transmission and arbitration delays, bus sizes in the case of a hybrid switch-bus network, packet size, and software overhead. The study used three algorithms to test the performance. The tested delta networks performed nearly equally showing that the model was stable. Next, the use of 2x2 switches was found to be somewhat superior to the use of 4x4 switch with the same amount of buffering per input. Increasing buffer size from one packet to two resulted in significant performance improvements, but further increases in buffer size did not. Depending on the amount of software overhead, it is not always necessary to have the fastest transmission possible through the network since the bottleneck on system performance is frequently the software overhead. In most cases, the high throughput of a LogN-stage MIN was unnecessary, and a hybrid network with busses having 16 processors gave acceptable performance. | |
| dc.format.extent | 130 p. | en_US |
| dc.format.mimetype | application/pdf | |
| dc.identifier.callno | Thesis E.E. 1990 Lauderdale | |
| dc.identifier.citation | Lauderdale, Grant Matthew. "Performance prediction of packet switched multistage interconnection networks in an execution-driven environment." (1990) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/13446">https://hdl.handle.net/1911/13446</a>. | |
| dc.identifier.uri | https://hdl.handle.net/1911/13446 | |
| dc.language.iso | eng | |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | |
| dc.subject | Electronics | |
| dc.subject | Electrical engineering | |
| dc.subject | Computer science | |
| dc.title | Performance prediction of packet switched multistage interconnection networks in an execution-driven environment | |
| dc.type | Thesis | |
| dc.type.material | Text | |
| thesis.degree.department | Electrical Engineering | |
| thesis.degree.discipline | Engineering | |
| thesis.degree.grantor | Rice University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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