Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder

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dc.citation.conferenceDate2013en_US
dc.citation.conferenceNameIEEE International Symposium on Circuits and Systems (ISCAS)en_US
dc.citation.firstpage1340
dc.citation.lastpage1343
dc.citation.locationBeijing, Chinaen_US
dc.contributor.authorWang, Guohui
dc.contributor.authorVosoughi, Aida
dc.contributor.authorShen, Hao
dc.contributor.authorCavallaro, Joseph R.
dc.contributor.authorGuo, Yuanbin
dc.date.accessioned2013-10-25T21:20:22Z
dc.date.available2013-10-25T21:20:22Z
dc.date.issued2013-05
dc.description.abstractParallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel interleaving address generation hardware very difficult to implement. In this paper, we propose a parallel interleaver architecture that can generate multiple interleaving addresses on-the-fly. We devised a novel scheduling scheme with which we can use more efficient buffer structures to eliminate memory contention. The synthesis results show that the proposed architecture with the new scheduling scheme can significantly reduce memory usage and hardware complexity. The proposed architecture also shows great flexibility and scalability compared to prior work.en_US
dc.description.sponsorshipUS National Science Foundation grant EECS-1232274en_US
dc.description.sponsorshipUS National Science Foundation grant EECS-0925942en_US
dc.description.sponsorshipUS National Science Foundation grant CNS-0923479en_US
dc.identifier.citationG. Wang, A. Vosoughi, H. Shen, J. R. Cavallaro and Y. Guo, "Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder," 2013.*
dc.identifier.doihttp://dx.doi.org/10.1109/ISCAS.2013.6572102en_US
dc.identifier.urihttps://hdl.handle.net/1911/75012
dc.language.isoengen
dc.publisherIEEEen_US
dc.subjectVLSIen_US
dc.subjectturbo decoderen_US
dc.subjectparallel interleaveren_US
dc.subjectHSPA+en_US
dc.subjecthigh throughputen_US
dc.subjectcontention-freeen_US
dc.subjectparallel processingen_US
dc.subjectmemory conflicten_US
dc.titleParallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoderen_US
dc.typeConference paperen_US
dc.type.dcmiTexten
dc.type.dcmiTexten_US
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