Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | Asilomar Conference on Signals, Systems, and Computers | en_US |
| dc.citation.firstpage | 2171 | en_US |
| dc.citation.lastpage | 2175 | en_US |
| dc.citation.location | Monterey, CA | en_US |
| dc.citation.volumeNumber | 2 | en_US |
| dc.contributor.author | Guo, Yuanbin | en_US |
| dc.contributor.author | McCain, Dennis | en_US |
| dc.contributor.author | Zhang, Jianzhong (Charlie) | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:45:47Z | en_US |
| dc.date.available | 2007-10-31T00:45:47Z | en_US |
| dc.date.issued | 2003-11-01 | en_US |
| dc.date.modified | 2005-03-09 | en_US |
| dc.date.note | 2003-12-20 | en_US |
| dc.date.submitted | 2003-11-01 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink re-ceivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz structure of the correlation matrix. A Pipelined-Multiplexing-Scheduler (PMS) is designed in the front-end to achieve scalable computation of the correlation coefficients. Very efficient VLSI architectures are designed by investigat-ing the multiple level parallelism and pipelining with a Precision-C based High-Level-Synthesis (HLS) design methodology. A 1Ã 2 Single-Input-Multiple-Output (SIMO) downlink receiver is designed and integrated in the HSDPA prototype system with Xilinx Virtex-II XC2V6000 FPGAs. The design demonstrates more area/time efficiency by achieving the best tradeoffs between the usage of functional units and real-time requirements. | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | Y. Guo, D. McCain, J. (. Zhang and J. R. Cavallaro, "Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink," vol. 2, 2003. | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/ACSSC.2003.1292365 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/19925 | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | FPGA | en_US |
| dc.subject | chip equalizer | en_US |
| dc.subject | SIMO | en_US |
| dc.subject | HSDPA | en_US |
| dc.subject.keyword | FPGA | en_US |
| dc.subject.keyword | chip equalizer | en_US |
| dc.subject.keyword | SIMO | en_US |
| dc.subject.keyword | HSDPA | en_US |
| dc.title | Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
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