Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameAsilomar Conference on Signals, Systems, and Computersen_US
dc.citation.firstpage2171
dc.citation.lastpage2175
dc.citation.locationMonterey, CAen_US
dc.citation.volumeNumber2en_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.authorMcCain, Dennisen_US
dc.contributor.authorZhang, Jianzhong (Charlie)en_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:45:47Z
dc.date.available2007-10-31T00:45:47Z
dc.date.issued2003-11-01
dc.date.modified2005-03-09en_US
dc.date.note2003-12-20en_US
dc.date.submitted2003-11-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractIn this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink re-ceivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz structure of the correlation matrix. A Pipelined-Multiplexing-Scheduler (PMS) is designed in the front-end to achieve scalable computation of the correlation coefficients. Very efficient VLSI architectures are designed by investigat-ing the multiple level parallelism and pipelining with a Precision-C based High-Level-Synthesis (HLS) design methodology. A 1Ã 2 Single-Input-Multiple-Output (SIMO) downlink receiver is designed and integrated in the HSDPA prototype system with Xilinx Virtex-II XC2V6000 FPGAs. The design demonstrates more area/time efficiency by achieving the best tradeoffs between the usage of functional units and real-time requirements.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationY. Guo, D. McCain, J. (. Zhang and J. R. Cavallaro, "Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink," vol. 2, 2003.
dc.identifier.doihttp://dx.doi.org/10.1109/ACSSC.2003.1292365en_US
dc.identifier.urihttps://hdl.handle.net/1911/19925
dc.language.isoeng
dc.publisherIEEEen_US
dc.subjectFPGA*
dc.subjectchip equalizer*
dc.subjectSIMO*
dc.subjectHSDPA*
dc.subject.keywordFPGAen_US
dc.subject.keywordchip equalizeren_US
dc.subject.keywordSIMOen_US
dc.subject.keywordHSDPAen_US
dc.titleScalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlinken_US
dc.typeConference paper
dc.type.dcmiText
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