Efficient VLSI architectures for matrix factorizations

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dc.contributor.advisorCavallaro, Joseph R.en_US
dc.creatorHemkumar, Nariankadu D.en_US
dc.date.accessioned2009-06-03T23:54:34Zen_US
dc.date.available2009-06-03T23:54:34Zen_US
dc.date.issued1994en_US
dc.description.abstractThe SVD (Singular Value Decomposition) is a critical matrix factorization in many real-time computations from an application domain which includes signal processing and robotics; and complex data matrices are encountered in engineering practice. This thesis advocates the use of CORDIC (Coordinate Rotation Digital Computer) arithmetic for parallel computation of the SVD/eigenvalue decomposition of arbitrary complex/Hermitian matrices using Jacobi-like algorithms on processor arrays. The algorithms and architectures derive from extending the theory of Jacobi-like matrix factorizations to multi-step and inexact pivot (2 x 2) sub-matrix diagonalizations. Based on the former approach of multi-step diagonalization, and using a two-sided 2 x 2 unitary transformation amenable to CORDIC termed ${\cal Q}$ transformation, it is shown that an arbitrary complex 2 x 2 matrix may be diagonalized in at most two ${\cal Q}$ transformations while one ${\cal Q}$ transformation is sufficient to diagonalize a 2 x 2 Hermitian matrix. Inexact diagonalizations from the use of approximations to the desired transformations have been advocated in the context of Jacobi-like algorithms for reasons of efficiency. Through a unifying parameterization of approximations, efficacy of diagonalizations and expected convergence behavior, more efficient schemes than those reported in the literature are proposed for 2 x 2 real, real symmetric and Hermitian matrices. Convergence behavior of the different methods was obtained by implementing the algorithms on the CM5 using C$\sp\*$ and CMSSL. All proposed algorithms are cast in ${\cal Q}$ transformations and CORDIC-based VLSI processor architectures for implementation of the methods are detailed in (non-redundant) CORDIC and the redundant and on-line enhancements to CORDIC. The overhead for the evaluation of the unitary transformations in all cases is minimal, thus enabling the efficient evaluation and/or application, and pipelined execution of the two-sided 2 x 2 unitary transformations on the different systolic arrays proposed in the literature for SVD and eigenvalue decompositions.en_US
dc.format.extent217 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.callnoTHESIS E.E. 1994 HEMKUMARen_US
dc.identifier.citationHemkumar, Nariankadu D.. "Efficient VLSI architectures for matrix factorizations." (1994) Diss., Rice University. <a href="https://hdl.handle.net/1911/16731">https://hdl.handle.net/1911/16731</a>.en_US
dc.identifier.urihttps://hdl.handle.net/1911/16731en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectElectronicsen_US
dc.subjectElectrical engineeringen_US
dc.subjectMathematicsen_US
dc.subjectComputer scienceen_US
dc.titleEfficient VLSI architectures for matrix factorizationsen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelDoctoralen_US
thesis.degree.nameDoctor of Philosophyen_US
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