Dynamic Assertion-Based Verification for SystemC

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dc.contributor.advisorVardi, Moshe Y.en_US
dc.creatorTabakov, Deianen_US
dc.date.accessioned2013-03-08T00:39:29Zen_US
dc.date.available2013-03-08T00:39:29Zen_US
dc.date.issued2011en_US
dc.description.abstractSystemC has emerged as a de facto standard modeling language for hardware and embedded systems. However, the current standard does not provide support for temporal specifications. Specifically, SystemC lacks a mechanism for sampling the state of the model at different types of temporal resolutions, for observing the internal state of modules, and for integrating monitors efficiently into the model's execution. This work presents a novel framework for specifying and efficiently monitoring temporal assertions of SystemC models that removes these restrictions. This work introduces new specification language primitives that (1) expose the inner state of the SystemC kernel in a principled way, (2) allow for very fine control over the temporal resolution, and (3) allow sampling at arbitrary locations in the user code. An efficient modular monitoring framework presented here allows the integration of monitors into the execution of the model, while at the same time incurring low overhead and allowing for easy adoption. Instrumentation of the user code is automated using Aspect-Oriented Programming techniques, thereby allowing the integration of user-code-level sample points into the monitoring framework. While most related approaches optimize the size of the monitors, this work focuses on minimizing the runtime overhead of the monitors. Different encoding configurations are identified and evaluated empirically using monitors synthesized from a large benchmark of random and pattern temporal specifications. The framework and approaches described in this dissertation allow the adoption of assertion-based verification for SystemC models written using various levels of abstraction, from system level to register-transfer level. An advantage of this work is that many existing specification languages call be adopted to use the specification primitives described here, and the framework can easily be integrated into existing implementations of SystemC.en_US
dc.format.extent178 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.callnoTHESIS COMP.SCI. 2011 TABAKOVen_US
dc.identifier.citationTabakov, Deian. "Dynamic Assertion-Based Verification for SystemC." (2011) Diss., Rice University. <a href="https://hdl.handle.net/1911/70465">https://hdl.handle.net/1911/70465</a>.en_US
dc.identifier.digitalTabakovDen_US
dc.identifier.urihttps://hdl.handle.net/1911/70465en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectApplied sciencesen_US
dc.subjectAssertion-based verificationen_US
dc.subjectSpecification languagesen_US
dc.subjectElectrical engineeringen_US
dc.subjectSystem scienceen_US
dc.subjectComputer scienceen_US
dc.titleDynamic Assertion-Based Verification for SystemCen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentComputer Scienceen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelDoctoralen_US
thesis.degree.nameDoctor of Philosophyen_US
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