ASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems in WCDMA Downlink

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE Vehicular Technology Conference (VTC)en_US
dc.citation.firstpage1735en_US
dc.citation.lastpage1739en_US
dc.citation.volumeNumber3en_US
dc.contributor.authorRadosavljevic, Predragen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorde Baynast, Alexandreen_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:58:16Zen_US
dc.date.available2007-10-31T00:58:16Zen_US
dc.date.issued2004-09-01en_US
dc.date.modified2005-04-25en_US
dc.date.note2005-04-22en_US
dc.date.submitted2004-09-01en_US
dc.descriptionConference paperen_US
dc.description.abstractThis paper presents a customized and flexible hardware implementation of linear iterative channel equalization algorithms for WCDMA downlink transmission in 3G wireless system with multiple transmit and receive antennas (MIMO system). Optimized (in terms of area and execution time) and power efficient Application Specific Instruction set Processors (ASIPs) based on Transport Triggered Architecture (TTA) are designed that can operate efficiently in slow and fast fading high scattering environments. The instruction set of TTA processors is extended with several user-defined operations specific for channel equalization algorithms that dramatically optimize the architecture solution for the physical layer of the mobile handset. The final results of presented design-space exploration method are the ASIP processors with low cost/performance ratio. Automatic software-hardware co-design flow for conversion of C application code into gate-level hardware design of ASIP architectures is also described. Implemented ASIP solutions achieve real time requirements for 3GPP wireless standard (1xEV-DV standard, in particular) with reasonable clock speed and power dissipation.en_US
dc.identifier.citationP. Radosavljevic, J. R. Cavallaro and A. de Baynast, "ASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems in WCDMA Downlink," vol. 3, 2004.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/VETECF.2004.1400332en_US
dc.identifier.urihttps://hdl.handle.net/1911/20205en_US
dc.language.isoengen_US
dc.subjectEqualizationen_US
dc.subjectMIMOen_US
dc.subjectASIPen_US
dc.subjectWCDMAen_US
dc.subject.keywordEqualizationen_US
dc.subject.keywordMIMOen_US
dc.subject.keywordASIPen_US
dc.subject.keywordWCDMAen_US
dc.titleASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems in WCDMA Downlinken_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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