Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards
| dc.citation.conferenceDate | 2008 | en_US |
| dc.citation.conferenceName | IEEE International Conference on Application-Specific System, Architectures and Processors (ASAP) | en_US |
| dc.citation.firstpage | 209 | |
| dc.citation.lastpage | 214 | |
| dc.citation.location | Leuven, Belgium | en_US |
| dc.contributor.author | Sun, Yang | |
| dc.contributor.author | Zhu, Yuming | |
| dc.contributor.author | Goel, Manish | |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-13T21:46:33Z | |
| dc.date.available | 2012-06-13T21:46:33Z | |
| dc.date.issued | 2008-07-01 | eng |
| dc.description.abstract | In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate. | en_US |
| dc.description.sponsorship | Texas Instruments Incorporated | en_US |
| dc.identifier.citation | Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro, "Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," 2008. | * |
| dc.identifier.doi | http://dx.doi.org/10.1109/ASAP.2008.4580180 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=793314942826133761&hl=en&as_sdt=0,44 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64264 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en_US |
| dc.subject | Clock rate | en_US |
| dc.subject | Multi-code turbo decoder | en_US |
| dc.subject | Interleaver | en_US |
| dc.title | Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |