FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameAsilomar Conference on Signals, Systems, and Computersen_US
dc.contributor.authorKarkooti, Marjanen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorDick, Chrisen_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:49:04Z
dc.date.available2007-10-31T00:49:04Z
dc.date.issued2005-11-01
dc.date.modified2006-03-08en_US
dc.date.note2006-03-08en_US
dc.date.submitted2005-11-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractThis paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 by 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13 M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.en_US
dc.identifier.citationM. Karkooti, J. R. Cavallaro and C. Dick, "FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," 2005.
dc.identifier.doihttp://dx.doi.org/10.1109/ACSSC.2005.1600043en_US
dc.identifier.urihttps://hdl.handle.net/1911/20001
dc.language.isoeng
dc.subjectFPGA*
dc.subjectMatrix inversion*
dc.subject.keywordFPGAen_US
dc.subject.keywordMatrix inversionen_US
dc.titleFPGA Implementation of Matrix Inversion Using QRD-RLS Algorithmen_US
dc.typeConference paper
dc.type.dcmiText
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