Phsyically Secure Cryptographic Hardware

dc.contributor.advisorYang, Kaiyuan
dc.creatorHe, Yan
dc.date.accessioned2022-09-29T15:26:47Z
dc.date.available2023-05-01T05:01:11Z
dc.date.created2022-05
dc.date.issued2022-01-27
dc.date.submittedMay 2022
dc.date.updated2022-09-29T15:26:47Z
dc.description.abstractWith the recent booming of Internet of Things (IoT) technology, people now have physical access to various mobile and embedded devices. A malicious party can bypass software security and gain valuable information through physical attacks. Therefore, the physical security of IoT hardware is becoming increasingly important. Side-channel attack (SCA) is one of the major security concerns. Attackers can gain information inside the chip through physical side channels, like power consumption, electro-magnetic (EM) radiation, timing, etc. Existing protections induce large performance and energy overhead, and usually require design-specific modifications. We propose and demonstrate prototype chips for a SCA-resistant, design agnostic, high-performance digital low drop-out regulator (DLDO). We show that the proposed design can not only achieve state-of-the-art regulation performance, it also improves >20000x Power-SCA resistance (MTD) of an AES engine with little design overheads. Secure key storage is another important issue. Traditionally, a permanent key is externally written in non-volatile memory (NVM). This approach is dubious both in its vulnerability to hostile attackers and its area and power utilization. Physically Unclonable Function (PUF), on the other hand, generates a unique key for each device, has a small area and power consumption, and is secure against various tampering methods. Previous PUFs have stability issues that require large design or testing costs to overcome. We propose Automatic and Self-Checking and Healing (ASCH) PUF with dual modes of operation that aims to achieve a fully stabilized PUF with reduced cost. Silicon prototype shows ASCH-PUF has a small design overhead, achieves 0% instability (BER) with no testing cost, and has >2x reduced masking ratio compared with previous approaches.
dc.embargo.terms2023-05-01
dc.format.mimetypeapplication/pdf
dc.identifier.citationHe, Yan. "Phsyically Secure Cryptographic Hardware." (2022) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/113457">https://hdl.handle.net/1911/113457</a>.
dc.identifier.urihttps://hdl.handle.net/1911/113457
dc.language.isoeng
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.
dc.subjectHardware Security
dc.subjectSide-Channel Analysis
dc.subjectPhysically Unclonable Function
dc.titlePhsyically Secure Cryptographic Hardware
dc.typeThesis
dc.type.materialText
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineEngineering
thesis.degree.grantorRice University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science
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