VLSI implementation of the multistage detector for next generation wideband CDMA receivers

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dc.citation.bibtexNamearticleen_US
dc.citation.firstpage21
dc.citation.issueNumber1-3en_US
dc.citation.journalTitleJournal of VLSI Signal Processingen_US
dc.citation.lastpage33
dc.citation.volumeNumber30en_US
dc.contributor.authorXu, Gangen_US
dc.contributor.authorRajagopal, Sridharen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorAazhang, Behnaamen_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:59:15Z
dc.date.available2007-10-31T00:59:15Z
dc.date.issued2002-03-20
dc.date.modified2003-11-09en_US
dc.date.submitted2001-09-18en_US
dc.descriptionJournal Paperen_US
dc.description.abstractThe multistage detection algorithm has been proposed as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time VLSI implementation of this detection algorithm in the uplink system, where we have achieved both high performance in interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. Under the assumption of BPSK modulation, the differences between the bit estimates from consecutive stages are 0 and ±2. Bypassing the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. However, the convergence of the algorithm is dependent on the number of users, the interference and the signal to noise ratio and hence, the detection has a variable execution time. By using just two stages of the differencing detector, we achieve predictable execution time with performance equivalent to at least eight stages of the regular multistage detector. A VLSI implementation of the differencing multistage detector is built to demonstrate the computational savings and the real-time performance potential. The detector, handling up to eight users with 12-bit fixed point precision, was fabricated using a 1.2 um CMOS technology and can process 190 Kbps/user for 8 users.en_US
dc.description.sponsorshipTexas Advanced Technology Programen_US
dc.description.sponsorshipNokiaen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationG. Xu, S. Rajagopal, J. R. Cavallaro and B. Aazhang, "VLSI implementation of the multistage detector for next generation wideband CDMA receivers," <i>Journal of VLSI Signal Processing,</i> vol. 30, no. 1-3, 2002.
dc.identifier.doihttp://dx.doi.org/10.1023/A:1014086523082en_US
dc.identifier.urihttps://hdl.handle.net/1911/20227
dc.language.isoeng
dc.publisherKluwer Academic Publishersen_US
dc.subjectCDMA*
dc.subjectmultiuser detection*
dc.subjectmultistage detector*
dc.subjectinteference cancellation*
dc.subjectreal-time implementation*
dc.subject.keywordCDMAen_US
dc.subject.keywordmultiuser detectionen_US
dc.subject.keywordmultistage detectoren_US
dc.subject.keywordinteference cancellationen_US
dc.subject.keywordreal-time implementationen_US
dc.titleVLSI implementation of the multistage detector for next generation wideband CDMA receiversen_US
dc.typeJournal article
dc.type.dcmiText
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