The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | International Symposium on High Performance Computer Architecture (HPCA) | en_US |
| dc.citation.firstpage | 72 | en_US |
| dc.citation.lastpage | 83 | en_US |
| dc.citation.location | San Antonio, TX | en_US |
| dc.contributor.author | Pai, Vijay S. | en_US |
| dc.contributor.author | Ranganathan, Parthasarathy | en_US |
| dc.contributor.author | Adve, Sarita V. | en_US |
| dc.contributor.org | CITI (http://citi.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:57:15Z | en_US |
| dc.date.available | 2007-10-31T00:57:15Z | en_US |
| dc.date.issued | 1997-02-20 | en_US |
| dc.date.modified | 2002-03-20 | en_US |
| dc.date.note | 2002-03-20 | en_US |
| dc.date.submitted | 1997-02-20 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | None | en_US |
| dc.identifier.citation | V. S. Pai, P. Ranganathan and S. V. Adve, "The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," 1997. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20181 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | instruction-level parallelism | en_US |
| dc.subject | shared-memory multiprocessors | en_US |
| dc.subject | performance evaluation | en_US |
| dc.subject.keyword | instruction-level parallelism | en_US |
| dc.subject.keyword | shared-memory multiprocessors | en_US |
| dc.subject.keyword | performance evaluation | en_US |
| dc.title | The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
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