The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameInternational Symposium on High Performance Computer Architecture (HPCA)en_US
dc.citation.firstpage72
dc.citation.lastpage83
dc.citation.locationSan Antonio, TXen_US
dc.contributor.authorPai, Vijay S.en_US
dc.contributor.authorRanganathan, Parthasarathyen_US
dc.contributor.authorAdve, Sarita V.en_US
dc.contributor.orgCITI (http://citi.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:57:15Z
dc.date.available2007-10-31T00:57:15Z
dc.date.issued1997-02-20
dc.date.modified2002-03-20en_US
dc.date.note2002-03-20en_US
dc.date.submitted1997-02-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractNoneen_US
dc.identifier.citationV. S. Pai, P. Ranganathan and S. V. Adve, "The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," 1997.
dc.identifier.urihttps://hdl.handle.net/1911/20181
dc.language.isoeng
dc.subjectinstruction-level parallelism*
dc.subjectshared-memory multiprocessors*
dc.subjectperformance evaluation*
dc.subject.keywordinstruction-level parallelismen_US
dc.subject.keywordshared-memory multiprocessorsen_US
dc.subject.keywordperformance evaluationen_US
dc.titleThe Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodologyen_US
dc.typeConference paper
dc.type.dcmiText
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