ASIP Architecture for Future Wireless Systems: Flexibility and Customization

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameWireless World Research Forum (WWRF)en_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorRadosavljevic, Predragen_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:38:29Zen_US
dc.date.available2007-10-31T00:38:29Zen_US
dc.date.issued2004-06-01en_US
dc.date.modified2004-08-30en_US
dc.date.note2004-05-14en_US
dc.date.submitted2004-06-01en_US
dc.descriptionConference paperen_US
dc.description.abstractEfficiency and flexibility are crucial features of the processors in the next generation of wireless cellular systems. Processors need to be efficient in order to satisfy real-time requirements for very demanding algorithms in new emerging wireless standards (3GPP, 4G, 802.11x, WiFi, DVD-S2, DAB, just to name a few). Flexibility, on the other hand, allows design modifications to respond to the evolution of standards (from GPRS to 3G, for example), worldwide compatibility (UMTS in Europe and Asia, CDMA2000 in North America), changes of user requirements depending of the quality of service (QoS), etc. Often, efficiency and flexibility goals are conflicting. Efficiency is related to the more custom hardware implementation such as ASIC processors. On the other hand, flexibility is the basic feature of programmable platforms such as DSP processors. While computationally efficient and low power solutions, ASIC processors for wireless applications are often not flexible enough to support necessary variations of implemented algorithms. ASIC design, especially in deep sub micron technologies, is very complex task and the manufacturing costs are also high. It is cheaper to write and debug software (application written in high level languages) than directly design, debug and manufacture hardware. Furthermore, there are increasing demands for products with low time-to-market, which is not primary characteristic of the ASIC design. On the other hand, DSP processor, although fully programmable, cannot achieve high performance with low power dissipation. DSP cores are often not able to achieve high level of instruction and data parallelism required for future generations of wireless systems.en_US
dc.description.sponsorshipNokiaen_US
dc.description.sponsorshipNokia/Texas Instrumentsen_US
dc.identifier.citationJ. R. Cavallaro and P. Radosavljevic, "ASIP Architecture for Future Wireless Systems: Flexibility and Customization," 2004.en_US
dc.identifier.urihttps://hdl.handle.net/1911/19762en_US
dc.language.isoengen_US
dc.subjectASIPen_US
dc.subject3GPPen_US
dc.subjectASICen_US
dc.subjectDSPen_US
dc.subjectFlexibilityen_US
dc.subjectCustomizationen_US
dc.subjectRetargetable Compileren_US
dc.subjectHardware Design Flowen_US
dc.subject.keywordASIPen_US
dc.subject.keyword3GPPen_US
dc.subject.keywordASICen_US
dc.subject.keywordDSPen_US
dc.subject.keywordFlexibilityen_US
dc.subject.keywordCustomizationen_US
dc.subject.keywordRetargetable Compileren_US
dc.subject.keywordHardware Design Flowen_US
dc.titleASIP Architecture for Future Wireless Systems: Flexibility and Customizationen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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