Novel dual-Vth independent-gate FinFET circuits
| dc.citation.firstpage | 867 | |
| dc.citation.lastpage | 872 | |
| dc.contributor.author | Rostami, Masoud | |
| dc.contributor.author | Mohanram, Kartik | |
| dc.date.accessioned | 2013-09-18T17:03:36Z | |
| dc.date.available | 2013-09-18T17:03:36Z | |
| dc.date.issued | 2010 | |
| dc.description.abstract | This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology. | en_US |
| dc.description.sponsorship | NSF CAREER Award CCF-0746850 | en_US |
| dc.identifier.citation | M. Rostami and K. Mohanram, "Novel dual-Vth independent-gate FinFET circuits," 2010. | * |
| dc.identifier.uri | https://hdl.handle.net/1911/72090 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en_US |
| dc.title | Novel dual-Vth independent-gate FinFET circuits | en_US |
| dc.type | Journal article | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |