Modelling Heterogeneous DSP–FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment
| dc.citation.conferenceDate | 2005 | en_US |
| dc.citation.conferenceName | 39th Asilomar Conference on Signals, Systems and Computers | en_US |
| dc.citation.firstpage | 1630 | |
| dc.citation.lastpage | 1634 | |
| dc.citation.location | Pacific Grove, CA | en_US |
| dc.contributor.author | Brogioli, Michael | |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-14T18:27:25Z | |
| dc.date.available | 2012-06-14T18:27:25Z | |
| dc.date.issued | 2005-11-01 | eng |
| dc.description.abstract | In this paper we present system-on-a-chip extensions to the Spinach simulation environment for rapidly prototyping heterogeneous DSP/FPGA based architectures, specifically in the embedded domain. This infrastructure has been successfully used to model systems varying from multiprocessor gigabit ethernet controllers to Texas Instruments C6x series DSP based systems with tightly coupled FPGA based coprocessors for computational offloading. As an illustrative example of this toolsets functionality, we investigate workload partitioning in heterogeneous DSP/FPGA based embedded environments. Specifically, we focus on computational offloading of matrix multiplication kernels across DSP/FPGA based embedded architectures. | en_US |
| dc.identifier.citation | M. Brogioli and J. R. Cavallaro, "Modelling Heterogeneous DSP–FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment," 2005. | * |
| dc.identifier.doi | http://dx.doi.org/10.1109/ACSSC.2005.1600044 | en_US |
| dc.identifier.other | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1600044&tag=1 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64273 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en_US |
| dc.subject | System-on-Chip | en_US |
| dc.subject | Rapid prototyping | en_US |
| dc.subject | DSP | en_US |
| dc.subject | Matrix multiplication kernels | en_US |
| dc.title | Modelling Heterogeneous DSP–FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |