Effective Techniques for Managing Intermediate-Sized Superpages

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dc.contributor.advisorCox, Alan Len_US
dc.creatorSolomon, Eliot Huttonen_US
dc.date.accessioned2024-08-30T18:38:23Zen_US
dc.date.created2024-08en_US
dc.date.issued2024-08-09en_US
dc.date.submittedAugust 2024en_US
dc.date.updated2024-08-30T18:38:23Zen_US
dc.descriptionEMBARGO NOTE: This item is embargoed until 2026-08-01en_US
dc.description.abstractTranslation lookaside buffers (TLBs) are pieces of hardware that cache the results of expensive address translations, improving the performance of the virtual memory system. Design constraints make it impossible for TLBs to store more than a few thousand entries, so "superpages" allow the operating system to instruct the TLB to cache a larger block of memory using a single entry. For small, frequently used memory objects like files and shared libraries, it can be difficult for the operating system to appropriately trade off the memory fragmentation induced by creating a 2 MB superpage with the performance benefits that doing so provides. Because of this, we investigate emerging hardware support for smaller “intermediate-sized” superpages. The first phase of our work explores PTE Coalescing, a feature of AMD Ryzen processors that transparently forms 16 KB or 32 KB superpages from aligned and contiguous groups of 4 KB base pages. We develop a custom microbenchmark to infer details of PTE Coalescing’s hardware implementation. We then determine that the contiguity generated by the Linux and FreeBSD physical memory allocators is insufficient to enable much coalescing and that reservation-based allocation is a good technique for generating additional contiguity to enhance PTE Coalescing. In the second phase of our work, we introduce the first production system capable of simultaneously managing two superpage sizes for file-backed and anonymous mappings by implementing support in the FreeBSD kernel for non-transparent 64 KB superpages on the ARM architecture using the latter’s Contiguous bit feature. We observe a 13.83% improvement in an exec() microbenchmark, a 6.83% boost in Node.js rendering performance, and a 11.18% speedup in a compilation-centric workload. More aggressive superpage promotion policies can further increase the performance benefits; we can boost the speedup to 15.67% using the right policy for the compilation-heavy workload.en_US
dc.embargo.lift2026-08-01en_US
dc.embargo.terms2026-08-01en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationSolomon, Eliot Hutton. Effective Techniques for Managing Intermediate-Sized Superpages. (2024). Masters thesis, Rice University. https://hdl.handle.net/1911/117838en_US
dc.identifier.urihttps://hdl.handle.net/1911/117838en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectcomputer systemsen_US
dc.subjectvirtual memoryen_US
dc.subjectaddress translationen_US
dc.subjectTLBen_US
dc.subjecttranslation lookaside bufferen_US
dc.subjecthuge pageen_US
dc.subjectsuperpageen_US
dc.subjectFreeBSDen_US
dc.titleEffective Techniques for Managing Intermediate-Sized Superpagesen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentComputer Scienceen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Scienceen_US
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