Design space exploration for real-time embedded stream processors

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dc.citation.bibtexNamearticleen_US
dc.citation.firstpage54en_US
dc.citation.issueNumber4en_US
dc.citation.journalTitleIEEE Microen_US
dc.citation.lastpage66en_US
dc.citation.volumeNumber24en_US
dc.contributor.authorRajagopal, Sridharen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorRixner, Scotten_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:59:40Zen_US
dc.date.available2007-10-31T00:59:40Zen_US
dc.date.issued2004-07-01en_US
dc.date.modified2005-11-17en_US
dc.date.submitted2004-03-21en_US
dc.descriptionJournal Paperen_US
dc.description.abstractWe present a design framework for rapidly exploring the design space for stream processors in real-time embedded systems. Stream processors enable hundreds of arithmetic units in programmable pro-cessors by using clusters of functional units. However, to meet a certain real-time requirement for an embedded system, there is a trade-off between the number of arithmetic units in a cluster, number of clusters and the clock frequency as each solution meets real-time with a different power consumption. We have developed a design exploration tool that explores this trade-off and presents a heuristic that minimizes the power consumption in the (functional units, clusters, frequency) design space. Our design methodology relates the instruction level parallelism, subword parallelism and data parallelism to the organization of the functional units in an embedded stream processor. We show that the power minimization methodology also provides insights into the functional unit utilization of the processor. The design exploration tool exploits the static nature of signal processing workloads, providing an extremely fast design space exploration and provides an initial lower bound estimate of the real-time performance of the embedded processor. A sensitivity analysis of the design tool results to the technology and modeling also enables the designer to check the robustness of the design exploration.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNokia/Texas Instrumentsen_US
dc.identifier.citationS. Rajagopal, J. R. Cavallaro and S. Rixner, "Design space exploration for real-time embedded stream processors," <i>IEEE Micro,</i> vol. 24, no. 4, 2004.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/MM.2004.25en_US
dc.identifier.urihttps://hdl.handle.net/1911/20236en_US
dc.language.isoengen_US
dc.relation.softwarehttp://www.ece.rice.edu/~sridhar/software.htmlen_US
dc.subjectdesign space explorationen_US
dc.subjectwireless systemsen_US
dc.subjectreal-timeen_US
dc.subjectlow poweren_US
dc.subjectdata parallelismen_US
dc.subjectinstruction level parallelismen_US
dc.subjectstream processorsen_US
dc.subject.keyworddesign space explorationen_US
dc.subject.keywordwireless systemsen_US
dc.subject.keywordreal-timeen_US
dc.subject.keywordlow poweren_US
dc.subject.keyworddata parallelismen_US
dc.subject.keywordinstruction level parallelismen_US
dc.subject.keywordstream processorsen_US
dc.titleDesign space exploration for real-time embedded stream processorsen_US
dc.typeJournal articleen_US
dc.type.dcmiTexten_US
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