Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors

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dc.citation.bibtexNamearticleen_US
dc.citation.firstpage769
dc.citation.issueNumber7en_US
dc.citation.journalTitleIEEE Transactions on Computersen_US
dc.citation.lastpage779
dc.citation.volumeNumber42en_US
dc.contributor.authorKota, Kishoreen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:50:42Z
dc.date.available2007-10-31T00:50:42Z
dc.date.issued1993-07-20
dc.date.modified2001-08-31en_US
dc.date.submitted2001-08-31en_US
dc.descriptionJournal Paperen_US
dc.description.abstractThe coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. It is desirable to use fixed-point CORDIC units in such systems, since the low complexity, compared to floating-point, allows multiple CORDIC units and additional hardware to be integrated on the same chip. However, an analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. This paper describes two approaches to tackle the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. This paper presents a method to integrate the normalization operation with the CORDIC iterations for efficient implementation in "0(n1.5)" hardware. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. We present arguments to support the use of such an architecture in certain special purpose arrays.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationK. Kota and J. R. Cavallaro, "Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors," <i>IEEE Transactions on Computers,</i> vol. 42, no. 7, 1993.
dc.identifier.doihttp://dx.doi.org/10.1109/12.237718en_US
dc.identifier.urihttps://hdl.handle.net/1911/20039
dc.language.isoeng
dc.subjectCORDIC*
dc.subjecterror analysis*
dc.subjecterror reduction*
dc.subjecthardware complexity*
dc.subjectVLSI*
dc.subject.keywordCORDICen_US
dc.subject.keyworderror analysisen_US
dc.subject.keyworderror reductionen_US
dc.subject.keywordhardware complexityen_US
dc.subject.keywordVLSIen_US
dc.titleNumerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processorsen_US
dc.typeJournal article
dc.type.dcmiText
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