Building a Control-flow Graph from Scheduled Assembly Code

Simple item page
dc.contributor.authorCooper, Keith D.en_US
dc.contributor.authorHarvey, Timothy J.en_US
dc.contributor.authorWaterman, Todden_US
dc.date.accessioned2017-08-02T22:02:57Zen_US
dc.date.available2017-08-02T22:02:57Zen_US
dc.date.issued2002-02-01en_US
dc.date.noteFebruary 1, 2002en_US
dc.description.abstractA variety of applications have arisen where it is worthwhile to apply code optimizations directly to the machine code (or assembly code) produced by a compiler. These include link-time whole-program analysis and optimization, code compression, binary- to-binary translation, and bit-transition reduction (for power). Many, if not most, optimizations assume the presence of a control-flow graph (cfg). Compiled, scheduled code has properties that can make cfg construction more complex than it is inside a typical compiler. In this paper, we examine the problems of scheduled code on architectures that have multiple delay slots. In particular, if branch delay slots contain other branches, the classic algorithms for building a cfg produce incorrect results. We explain the problem using two simple examples. We then present an algorithm for building correct cfgs from scheduled assembly code that includes branches in branch-delay slots. The algorithm works by building an approximate cfg and then refining it to reflect the actions of delayed branches. If all branches have explicit targets, the complexity of the refining step is linear with respect to the number of branches in the code. Analysis of the kind presented in this paper is a necessary first step for any system that analyzes or translates compiled, assembly-level code. We have implemented this algorithm in our power-consumption experiments based on the TMS320C6200 architecture from Texas Instruments. The development of our algorithm was motivated by the output of TI’s compiler.en_US
dc.format.extent10 ppen_US
dc.identifier.citationCooper, Keith D., Harvey, Timothy J. and Waterman, Todd. "Building a Control-flow Graph from Scheduled Assembly Code." (2002) https://hdl.handle.net/1911/96303.en_US
dc.identifier.digitalTR02-399en_US
dc.identifier.urihttps://hdl.handle.net/1911/96303en_US
dc.language.isoengen_US
dc.rightsYou are granted permission for the noncommercial reproduction, distribution, display, and performance of this technical report in any format, but this permission is only for a period of forty-five (45) days from the most recent time that you verified that this technical report is still available from the Computer Science Department of Rice University under terms that include this permission. All other rights are reserved by the author(s).en_US
dc.titleBuilding a Control-flow Graph from Scheduled Assembly Codeen_US
dc.typeTechnical reporten_US
dc.type.dcmiTexten_US
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
TR02-399.pdf
Size:
222.11 KB
Format:
Adobe Portable Document Format
Download
Collections
Computer Science Technical Reports