Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) | en_US |
| dc.citation.firstpage | 173 | |
| dc.citation.lastpage | 184 | |
| dc.contributor.author | Rajagopal, Sridhar | en_US |
| dc.contributor.author | Bhashyam, Srikrishna | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.author | Aazhang, Behnaam | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:58:51Z | |
| dc.date.available | 2007-10-31T00:58:51Z | |
| dc.date.issued | 2000-07-20 | en |
| dc.date.modified | 2003-11-10 | en_US |
| dc.date.note | 2001-08-18 | en_US |
| dc.date.submitted | 2000-07-20 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | A real-time VLSI architecture is designed for multiuser channel estimation, one of the core base-band processing operations in wireless base-station receivers. Future wireless basestation receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP architectures are unable to fully exploit the parallelism and bit level arithmetic present in these algorithms. These features can be revealed and efficiently implemented by task partitioning the algorithms for a VLSI solution. We modify the channel estimation algorithm for a reduced complexity fixed-point hardware implementation. We show the complexity and hardware required for three different area-time tradeoffs: an area-constrained, a time-constrained and an area-time efficient architecture. The area-constrained architecture achieves low data rates with minimum hardware, which may be used in picocell base-stations. The time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data rates. The area-time efficient architecture meets real-time requirements with minimum area overhead. The orders-of-magnitude difference between area and time constrained solutions reveals significant inherent parallelism in the algorithm. All proposed VLSI solutions exhibit better time performance than a previous DSP implementation. | en_US |
| dc.description.sponsorship | Texas Advanced Technology Program | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," 2000. | |
| dc.identifier.doi | http://dx.doi.org/10.1109/ASAP.2000.862388 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20218 | |
| dc.language.iso | eng | |
| dc.subject | VLSI architectures | * |
| dc.subject | baseband signal processing | * |
| dc.subject | wireless base-station receivers | * |
| dc.subject | DSP | * |
| dc.subject.keyword | VLSI architectures | en_US |
| dc.subject.keyword | baseband signal processing | en_US |
| dc.subject.keyword | wireless base-station receivers | en_US |
| dc.subject.keyword | DSP | en_US |
| dc.title | Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers | en_US |
| dc.type | Conference paper | |
| dc.type.dcmi | Text |