Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)en_US
dc.citation.firstpage173en_US
dc.citation.lastpage184en_US
dc.contributor.authorRajagopal, Sridharen_US
dc.contributor.authorBhashyam, Srikrishnaen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorAazhang, Behnaamen_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:58:51Zen_US
dc.date.available2007-10-31T00:58:51Zen_US
dc.date.issued2000-07-20en_US
dc.date.modified2003-11-10en_US
dc.date.note2001-08-18en_US
dc.date.submitted2000-07-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractA real-time VLSI architecture is designed for multiuser channel estimation, one of the core base-band processing operations in wireless base-station receivers. Future wireless basestation receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP architectures are unable to fully exploit the parallelism and bit level arithmetic present in these algorithms. These features can be revealed and efficiently implemented by task partitioning the algorithms for a VLSI solution. We modify the channel estimation algorithm for a reduced complexity fixed-point hardware implementation. We show the complexity and hardware required for three different area-time tradeoffs: an area-constrained, a time-constrained and an area-time efficient architecture. The area-constrained architecture achieves low data rates with minimum hardware, which may be used in picocell base-stations. The time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data rates. The area-time efficient architecture meets real-time requirements with minimum area overhead. The orders-of-magnitude difference between area and time constrained solutions reveals significant inherent parallelism in the algorithm. All proposed VLSI solutions exhibit better time performance than a previous DSP implementation.en_US
dc.description.sponsorshipTexas Advanced Technology Programen_US
dc.description.sponsorshipNokiaen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationS. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," 2000.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/ASAP.2000.862388en_US
dc.identifier.urihttps://hdl.handle.net/1911/20218en_US
dc.language.isoengen_US
dc.subjectVLSI architecturesen_US
dc.subjectbaseband signal processingen_US
dc.subjectwireless base-station receiversen_US
dc.subjectDSPen_US
dc.subject.keywordVLSI architecturesen_US
dc.subject.keywordbaseband signal processingen_US
dc.subject.keywordwireless base-station receiversen_US
dc.subject.keywordDSPen_US
dc.titleEfficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receiversen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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