ShuFFLE: Automated Framework for HArdware Accelerated Iterative Big Data Analysis

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dc.contributor.advisorKoushanfar, Farinazen_US
dc.contributor.committeeMemberBaraniuk, Richarden_US
dc.contributor.committeeMemberCavallaro, Josephen_US
dc.creatorMohammadgholi Songhori, Ebrahimen_US
dc.date.accessioned2016-01-28T22:01:47Zen_US
dc.date.available2016-01-28T22:01:47Zen_US
dc.date.created2014-12en_US
dc.date.issued2014-10-22en_US
dc.date.submittedDecember 2014en_US
dc.date.updated2016-01-28T22:01:47Zen_US
dc.description.abstractThis thesis introduces ShuFFLE, a set of novel methodologies and tools for automated analysis and hardware acceleration of large and dense (non-sparse) Gram matrices. Such matrices arise in most contemporary data mining; they are hard to handle because of the complexity of known matrix transformation algorithms and the inseparability of non-sparse correlations. ShuFFLE learns the properties of the Gram matrices and their rank for each particular application domain. It then utilizes the underlying properties for reconfiguring accelerators that scalably operate on the data in that domain. The learning is based on new factorizations that work at the limit of the matrix rank to optimize the hardware implementation by minimizing the costly off-chip memory as well as I/O interactions. ShuFFLE also provides users with a new Application Programming Interface (API) to implement a customized iterative least squares solver for analyzing big and dense matrices in a scalable way. This API is readily integrated within the Xilinx Vivado High Level Synthesis tool to translate user's code to Hardware Description Language (HDL). As a case study, we implement Fast Iterative Shrinkage-Thresholding Algorithm (FISTA) as an l1 regularized least squares solver. Experimental results show that during FISTA computation using Field-Programmable Gate Array (FPGA) platform, ShuFFLE attains 1800x iteration speed improvement compared to the conventional solver and about 24x improvement compared to our factorized solver on a general purpose processor with SSE4 architecture for a Gram matrix with 4.6 billion non-zero elements.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationMohammadgholi Songhori, Ebrahim. "ShuFFLE: Automated Framework for HArdware Accelerated Iterative Big Data Analysis." (2014) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/88235">https://hdl.handle.net/1911/88235</a>.en_US
dc.identifier.urihttps://hdl.handle.net/1911/88235en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectIterative Solveren_US
dc.subjectLeast Squaresen_US
dc.subjectFPGAsen_US
dc.subjectSparse Factorizationen_US
dc.subjectFISTAen_US
dc.subjectHLSen_US
dc.subjectDense Matrixen_US
dc.subjectAPIen_US
dc.titleShuFFLE: Automated Framework for HArdware Accelerated Iterative Big Data Analysisen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentElectrical and Computer Engineeringen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Scienceen_US
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