The performance of MOSFET's fabricated in LPCVD polysilicon thin films and operating in the accumulation mode is modeled analytically. The model is not a single crystal analogue but explains device operational characteristics in terms of intrinsic polysilicon structural and electronic properties and extrinsic operating conditions. The model describes transconductance, drain admittance, sub-threshold slope, current ON/OFF ratio and channel electrostatics as a function of grain size, substrate temperature, channel implant dose, film thickness, grain boundary trap density and level. This formulation introduces a new concept--that of electrostatic shielding of ionized dopants by mobile charges accumulated in the channel under the stimulus of an applied voltage. Consequently a feature unique to such devices is brought to fare whereby it is shown that the channel mobility becomes a function of the gate voltage. Overall device behavior is shown to exhibit three characteristically distinct regimes of operation namely--leakage, sub-threshold or weak accumulation and drive. In the former the current level is determined solely by the carrier lifetime and generation--recombinations rate within the polycrystalline silicon film. Whereas in the latter regimes a gate voltage induced mobility enhancement is shown to be primarily responsible in governing the device transconductance. This formulation explains experimentally observed characteristics at and above room temperature, both in devices fabricated in as deposited and in hydrogenated LPCVD polycrystalline silicon films. To the best of our knowledge this is the first comprehensive model describing the modus operandi of accumulation mode MOSFET's in polycrystalline silicon films.