FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | Asilomar Conference on Signals, Systems, and Computers | en_US |
| dc.citation.firstpage | 1625 | en_US |
| dc.citation.lastpage | 1629 | en_US |
| dc.contributor.author | Karkooti, Marjan | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.author | Dick, Chris | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:49:07Z | en_US |
| dc.date.available | 2007-10-31T00:49:07Z | en_US |
| dc.date.issued | 2005-10-01 | en_US |
| dc.date.modified | 2006-05-25 | en_US |
| dc.date.note | 2006-05-25 | en_US |
| dc.date.submitted | 2005-10-01 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 Ã 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes. | en_US |
| dc.identifier.citation | M. Karkooti, J. R. Cavallaro and C. Dick, "FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," 2005. | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/ACSSC.2005.1600043 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20002 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | QRD implementation | en_US |
| dc.subject | Squared Givens Rotation | en_US |
| dc.subject.keyword | QRD implementation | en_US |
| dc.subject.keyword | Squared Givens Rotation | en_US |
| dc.title | FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
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