VLSI Implementation of Mallat's Fast Discrete Wavelet

dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameGlobecomen_US
dc.citation.firstpage320en_US
dc.citation.lastpage324en_US
dc.citation.locationSan Antonio, TXen_US
dc.citation.volumeNumber1en_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.authorZhang, Hongzhouen_US
dc.contributor.authorWang, Xuguangen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:45:32Zen_US
dc.date.available2007-10-31T00:45:32Zen_US
dc.date.issued2001-11-20en_US
dc.date.modified2003-12-02en_US
dc.date.note2002-02-10en_US
dc.date.submitted2001-11-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractThis paper proposes a novel VLSI architecture to compute the DWT (discrete wavelet transform) coefficients using Mallat's algorithm with reduced complexity. We studied the commonality embedded in the mirror filters of the algorithm and use a PLA as an Address Generator (PAG) to load the data for cascaded FIR computation. By using an embedded downsampling process in the control signal design, we reduced the complexity by saving storage and computation. The prototyping design is implemented and fabricated using AMI 1.5 micron CMOS process through MOSIS.en_US
dc.identifier.citationY. Guo, H. Zhang, X. Wang and J. R. Cavallaro, "VLSI Implementation of Mallat's Fast Discrete Wavelet," vol. 1, 2001.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/GLOCOM.2001.965131en_US
dc.identifier.urihttps://hdl.handle.net/1911/19919en_US
dc.language.isoengen_US
dc.subjectVLSIen_US
dc.subjectDWTen_US
dc.subjectMallaten_US
dc.subject.keywordVLSIen_US
dc.subject.keywordDWTen_US
dc.subject.keywordMallaten_US
dc.titleVLSI Implementation of Mallat's Fast Discrete Waveleten_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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