Exploiting instruction-level parallelism for memory system performance

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dc.contributor.advisorAdve, Sarita V.en_US
dc.creatorPai, Vijay Sadanandaen_US
dc.date.accessioned2009-06-04T08:26:38Zen_US
dc.date.available2009-06-04T08:26:38Zen_US
dc.date.issued2000en_US
dc.description.abstractCurrent microprocessors improve performance by exploiting instruction-level parallelism (ILP). ILP hardware techniques such as multiple instruction issue, out-of-order (dynamic) issue, and non-blocking reads can accelerate both computation and data memory references. Since computation speeds have been improving faster than data memory access times, memory system performance is quickly becoming the primary obstacle to achieving high performance. This dissertation focuses on exploiting ILP techniques to improve memory system performance. This dissertation includes both an analysis of ILP memory system performance and optimizations developed using the insights of this analysis. First, this dissertation shows that ILP hardware techniques, used in isolation, are often unsuccessful at improving memory system performance because they fail to extract parallelism among data reads that miss in the processor's caches. The previously-studied latency-tolerance technique of software prefetching provides some improvement by initiating data read misses earlier, but also suffers from limitations caused by exposed startup latencies, excessive fetch-ahead distances, and references that are hard to prefetch. This dissertation then uses the above insights to develop compile-time software transformations that improve memory system parallelism and performance. These transformations improve the effectiveness of ILP hardware, reducing exposed latency by over 80% for a latency-detection microbenchmark and reducing execution time an average of 25% across 14 multiprocessor and uniprocessor cases studied in simulation and an average of 21% across 12 cases on a real system. These transformations also combine with software prefetching to address key limitations in either latency-tolerance technique alone, providing the best performance when both techniques are combined for most of the uniprocessor and multiprocessor codes that we study. Finally, this dissertation also explores appropriate evaluation methodologies for ILP shared-memory multiprocessors. Memory system parallelism is a key feature determining ILP performance, but is neglected in previous-generation fast simulators. This dissertation highlights the errors possible in such simulators and presents new evaluation methodologies to improve the tradeoff between accuracy and evaluation speed.en_US
dc.format.extent139 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.callnoTHESIS E.E. 2001 PAIen_US
dc.identifier.citationPai, Vijay Sadananda. "Exploiting instruction-level parallelism for memory system performance." (2000) Diss., Rice University. <a href="https://hdl.handle.net/1911/18009">https://hdl.handle.net/1911/18009</a>.en_US
dc.identifier.urihttps://hdl.handle.net/1911/18009en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectElectronicsen_US
dc.subjectElectrical engineeringen_US
dc.subjectComputer scienceen_US
dc.titleExploiting instruction-level parallelism for memory system performanceen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelDoctoralen_US
thesis.degree.nameDoctor of Philosophyen_US
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