GPU-based Acceleration of Symbol Timng Recovery
| dc.citation.conferenceDate | 2012 | en_US |
| dc.citation.conferenceName | Conference on Design and Architectures for Signal and Image Processing (DASIP) | en_US |
| dc.citation.location | Karlsruhe, Germany | en_US |
| dc.contributor.author | Kim, Scott C. | en_US |
| dc.contributor.author | Plishker, William L. | en_US |
| dc.contributor.author | Bhattacharyya, Shuvra S. | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | CMC | en_US |
| dc.date.accessioned | 2013-01-11T22:18:07Z | en_US |
| dc.date.available | 2013-01-11T22:18:07Z | en_US |
| dc.date.issued | 2012-12-20 | en_US |
| dc.description.abstract | This paper presents a novel implementation of graphics processing unit (GPU) based symbol timing recovery using polyphase interpolators to detect symbol timing error. Symbol timing recovery is a compute intensive procedure that detects and corrects the timing error in a coherent receiver. We provide optimal sample-time timing recovery using a maximum likelihood (ML) estimator to minimize the timing error. This is an iterative and adaptive system that relies on feedback, therefore, we present an accelerated implementation design by using a GPU for timing error detection (TED), enabling fast error detection by exploiting the 2D filter structure found in the polyphase interpolator. We present this hybrid/ heterogeneous CPU and GPU architecture by computing a low complexity and low noise matched filter (MF) while simultaneously performing TED. We then compare the performance of the CPU vs. GPU based timing recovery for different interpolation rates to minimize the error and improve the detection by up to a factor of 35. We further improve the process by utilizing GPU optimization and performing block processing to improve the throughput even more, all while maintaining the lowest possible sampling rate. | en_US |
| dc.description.sponsorship | Laboratory for Telecommunications Sciences | en_US |
| dc.description.sponsorship | National Science Foundation (NSF) | en_US |
| dc.identifier.citation | S. C. Kim, W. L. Plishker, S. S. Bhattacharyya and J. R. Cavallaro, "GPU-based Acceleration of Symbol Timng Recovery," 2012. | en_US |
| dc.identifier.isbn | 978-1-4673-2089-4 | en_US |
| dc.identifier.other | E-ISBN : 978-2-9539987-4-0 | en_US |
| dc.identifier.other | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6385393 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?hl=en&q=GPU-BASED+ACCELERATION+OF+SYMBOL+TIMING+RECOVERY&btnG=&as_sdt=1%2C44&as_sdtp= | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/69483 | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | GPU | en_US |
| dc.subject | symbol timing recovery | en_US |
| dc.subject | synchronization | en_US |
| dc.subject | coherent receiver design | en_US |
| dc.subject | DSP accelerator | en_US |
| dc.title | GPU-based Acceleration of Symbol Timng Recovery | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
| dc.type.dcmi | Text | en_US |