Register Organization for Media Processing

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameInternational Symposium on High Performance Computer Architecture (HPCA)en_US
dc.citation.firstpage375
dc.citation.lastpage386
dc.citation.locationToulouse, Franceen_US
dc.contributor.authorRixner, Scotten_US
dc.contributor.authorDally, William J.en_US
dc.contributor.authorKhailany, Bruceken_US
dc.contributor.authorMattson, Peteren_US
dc.contributor.authorKapasi, Ujval J.en_US
dc.contributor.authorOwens, John D.en_US
dc.date.accessioned2007-10-31T01:01:38Z
dc.date.available2007-10-31T01:01:38Z
dc.date.issued2000-01-20
dc.date.modified2002-03-28en_US
dc.date.note2002-03-28en_US
dc.date.submitted2000-01-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractProcessor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, and image understanding, require arithmetic rates of up to 10^11 operations per second. As the number of arithmetic units in a processor increases to meet these demands, register storage and communication between the arithmetic units dominate the area, delay, and power of the arithmetic units. In this paper we show that partitioning the register file along three axes reduces the cost of register storage and communication without significantly impacting performance. We develop a taxonomy of register architectures by partitioning across the data-parallel, instruction-level parallel, and memory hierarchy axes, and by optimizing the hierarchical register organization to operate on streams of data. Compared to a centralized global register file, the most compact of these organizations reduces the register file area, delay, and power dissipation of a media processor by factors of 195, 20, and 430, respectively. This reduction in cost is achieved with a performance degradation of only 8% on a representative set of media processing benchmarks.en_US
dc.identifier.citationS. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi and J. D. Owens, "Register Organization for Media Processing," 2000.
dc.identifier.urihttps://hdl.handle.net/1911/20278
dc.language.isoeng
dc.subjectmedia processing*
dc.subjectregister files*
dc.subjectprocessor architecture*
dc.subject.keywordmedia processingen_US
dc.subject.keywordregister filesen_US
dc.subject.keywordprocessor architectureen_US
dc.titleRegister Organization for Media Processingen_US
dc.typeConference paper
dc.type.dcmiText
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