Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding

Simple item page
dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameInternational Conference on Information Technology(ITCC)en_US
dc.citation.firstpage579
dc.citation.lastpage585
dc.citation.volumeNumber1en_US
dc.contributor.authorKarkooti, Marjanen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:49:00Z
dc.date.available2007-10-31T00:49:00Z
dc.date.issued2004-04-01
dc.date.modified2004-08-30en_US
dc.date.note2004-02-16en_US
dc.date.submitted2004-04-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractThis paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3,6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.en_US
dc.description.sponsorshipNokiaen_US
dc.description.sponsorshipNokia/Texas Instrumentsen_US
dc.description.sponsorshipNational Instrumentsen_US
dc.identifier.citationM. Karkooti and J. R. Cavallaro, "Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding," vol. 1, 2004.
dc.identifier.doihttp://dx.doi.org/10.1109/ITCC.2004.1286526en_US
dc.identifier.urihttps://hdl.handle.net/1911/19999
dc.language.isoeng
dc.subjectReconfigurable architecture*
dc.subjectFPGA implementation*
dc.subjectChannel coding*
dc.subjectParallel architecture*
dc.subjectArea-time tradeoffs*
dc.subject.keywordReconfigurable architectureen_US
dc.subject.keywordFPGA implementationen_US
dc.subject.keywordChannel codingen_US
dc.subject.keywordParallel architectureen_US
dc.subject.keywordArea-time tradeoffsen_US
dc.titleSemi-parallel Reconfigurable Architectures for Real-time LDPC Decodingen_US
dc.typeConference paper
dc.type.dcmiText
Files
Original bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
Kar2004Apr5Semiparall.PS
Size:
1.25 MB
Format:
Postscript Files
Download
Collections
ECE Publications