The design of a scalable, hierarchical-bus, shared-memory multiprocessor
| dc.contributor.advisor | Bennett, John K. | en_US |
| dc.creator | Greenwood, Jay Alan | en_US |
| dc.date.accessioned | 2009-06-03T23:52:51Z | en_US |
| dc.date.available | 2009-06-03T23:52:51Z | en_US |
| dc.date.issued | 1992 | en_US |
| dc.description.abstract | The hierarchical-bus architecture is an attractive solution to many of the problems associated with connecting processors together into a multiprocessing system but it also poses a number of design challenges. This thesis evaluates several architectural features of a hierarchical-bus multiprocessor. Our results show that applications with significant amounts of shared data achieve higher performance when run on a multiprocessor with a hierarchy of buses than on a single-bus multiprocessor. Also, applications with a significant number of write accesses to private data perform better using a cache protocol that modifies data within the cache (a copy-back protocol). This thesis describes a copy-back protocol for a hierarchical-bus multiprocessor and compares it with a cache protocol that broadcasts writes on the bus (a write-through protocol). | en_US |
| dc.format.extent | 78 p. | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.callno | Thesis E.E. 1992 Greenwood | en_US |
| dc.identifier.citation | Greenwood, Jay Alan. "The design of a scalable, hierarchical-bus, shared-memory multiprocessor." (1992) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/13618">https://hdl.handle.net/1911/13618</a>. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/13618 | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | en_US |
| dc.subject | Computer science | en_US |
| dc.subject | Electronics | en_US |
| dc.subject | Electrical engineering | en_US |
| dc.title | The design of a scalable, hierarchical-bus, shared-memory multiprocessor | en_US |
| dc.type | Thesis | en_US |
| dc.type.material | Text | en_US |
| thesis.degree.department | Electrical Engineering | en_US |
| thesis.degree.discipline | Engineering | en_US |
| thesis.degree.grantor | Rice University | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science | en_US |
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