Novel dual-threshold voltage FinFETs for circuit design and optimization

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dc.contributor.advisorMohanram, Kartiken_US
dc.creatorRostami, Masouden_US
dc.date.accessioned2013-03-08T00:38:11Zen_US
dc.date.available2013-03-08T00:38:11Zen_US
dc.date.issued2011en_US
dc.description.abstractA great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology.en_US
dc.format.extent49 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationRostami, Masoud. "Novel dual-threshold voltage FinFETs for circuit design and optimization." (2011) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/70416">https://hdl.handle.net/1911/70416</a>.en_US
dc.identifier.digitalRostamiMen_US
dc.identifier.urihttps://hdl.handle.net/1911/70416en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectApplied sciencesen_US
dc.subjectComputer engineeringen_US
dc.titleNovel dual-threshold voltage FinFETs for circuit design and optimizationen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentElectrical and Computer Engineeringen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Scienceen_US
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