Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors

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dc.citation.bibtexNamearticleen_US
dc.citation.firstpage40
dc.citation.issueNumber2en_US
dc.citation.journalTitleIEEE Computeren_US
dc.citation.lastpage49
dc.citation.volumeNumber35en_US
dc.contributor.authorHughes, Christopher J.en_US
dc.contributor.authorPai, Vijay S.en_US
dc.contributor.authorRanganathan, Parthasarathyen_US
dc.contributor.authorAdve, Sarita V.en_US
dc.contributor.orgCITI (http://citi.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:47:12Z
dc.date.available2007-10-31T00:47:12Z
dc.date.issued2002-02-20
dc.date.modified2002-03-20en_US
dc.date.submitted2002-03-20en_US
dc.descriptionJournal Paperen_US
dc.description.abstractRsim is a publicly available architecture simulator for shared-memory systems built from processors that aggressively exploit instruction-level parallelism. Modeling ILP features in a multiprocessor is particularly important for applications that exhibit parallelism among read misses.en_US
dc.identifier.citationC. J. Hughes, V. S. Pai, P. Ranganathan and S. V. Adve, "Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors," <i>IEEE Computer,</i> vol. 35, no. 2, 2002.
dc.identifier.doihttp://dx.doi.org/10.1109/2.982915en_US
dc.identifier.urihttps://hdl.handle.net/1911/19959
dc.language.isoeng
dc.subjectperformance evaluation*
dc.subjectmemory parallelism*
dc.subjectinstruction-level parallelism*
dc.subjectshared-memory multiprocessors*
dc.subject.keywordperformance evaluationen_US
dc.subject.keywordmemory parallelismen_US
dc.subject.keywordinstruction-level parallelismen_US
dc.subject.keywordshared-memory multiprocessorsen_US
dc.titleRsim: Simulating Shared-Memory Multiprocessors with ILP Processorsen_US
dc.typeJournal article
dc.type.dcmiText
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