A Bandwidth-Efficient Architecture for Media Processing

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE/ACM International Symposium on Microarchitecture (MICRO)en_US
dc.citation.firstpage3
dc.citation.lastpage13
dc.citation.locationDallas, TXen_US
dc.contributor.authorRixner, Scotten_US
dc.contributor.authorDally, William J.en_US
dc.contributor.authorKapasi, Ujval J.en_US
dc.contributor.authorKhailany, Bruceken_US
dc.contributor.authorLopez-Lagunas, Abelardoen_US
dc.contributor.authorMattson, Peteren_US
dc.contributor.authorOwens, John D.en_US
dc.date.accessioned2007-10-31T01:01:36Z
dc.date.available2007-10-31T01:01:36Z
dc.date.issued1998-11-20
dc.date.modified2002-03-28en_US
dc.date.note2002-03-28en_US
dc.date.submitted1998-11-20en_US
dc.descriptionConference paperen_US
dc.description.abstractMedia applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are poorly matched to conventional microprocessor architectures, they are a good fit for modern VLSI technology with its high arithmetic capacity but limited global bandwidth. The stream programming model, in which an application is coded as streams of data records passing through computation kernels, exposes both parallelism and locality in media applications that can be exploited by VLSI architectures. The Imagine architecture supports the stream programming model by providing a bandwidth hierarchy tailored to the demands of media applications. Compared to a conventional scalar processor, Imagine reduces the global register and memory bandwidth required by typical applications by factors of 13 and 21 respectively. This bandwidth efficiency enables a single chip Imagine processor to achieve a peak performance of 16.2GFLOPS (single-precision floating point) and sustained performance of up to 8.5GFLOPS on media processing kernels.en_US
dc.identifier.citationS. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. Mattson and J. D. Owens, "A Bandwidth-Efficient Architecture for Media Processing," 1998.
dc.identifier.urihttps://hdl.handle.net/1911/20277
dc.language.isoeng
dc.subjectmedia processing*
dc.subjectstream processing*
dc.subjectprocessor architecture*
dc.subject.keywordmedia processingen_US
dc.subject.keywordstream processingen_US
dc.subject.keywordprocessor architectureen_US
dc.titleA Bandwidth-Efficient Architecture for Media Processingen_US
dc.typeConference paper
dc.type.dcmiText
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