Memory Access Scheduling
dc.citation.bibtexName | inproceedings | en_US |
dc.citation.conferenceName | International Symposium on Computer Architecture (ISCA) | en_US |
dc.citation.firstpage | 128 | |
dc.citation.lastpage | 138 | |
dc.citation.location | Vancouver, B.C., Canada | en_US |
dc.contributor.author | Rixner, Scott | en_US |
dc.contributor.author | Dally, William J. | en_US |
dc.contributor.author | Kapasi, Ujval J. | en_US |
dc.contributor.author | Mattson, Peter | en_US |
dc.contributor.author | Owens, John D. | en_US |
dc.date.accessioned | 2007-10-31T01:01:40Z | |
dc.date.available | 2007-10-31T01:01:40Z | |
dc.date.issued | 2000-06-20 | |
dc.date.modified | 2002-03-28 | en_US |
dc.date.note | 2002-03-28 | en_US |
dc.date.submitted | 2000-06-20 | en_US |
dc.description | Conference Paper | en_US |
dc.description.abstract | The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the "3-D" structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth. | en_US |
dc.identifier.citation | S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson and J. D. Owens, "Memory Access Scheduling," 2000. | |
dc.identifier.uri | https://hdl.handle.net/1911/20279 | |
dc.language.iso | eng | |
dc.subject | memory system architecture | * |
dc.subject | DRAM organization | * |
dc.subject | media processing | * |
dc.subject.keyword | memory system architecture | en_US |
dc.subject.keyword | DRAM organization | en_US |
dc.subject.keyword | media processing | en_US |
dc.title | Memory Access Scheduling | en_US |
dc.type | Conference paper | |
dc.type.dcmi | Text |
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