Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | International Conference on Signal Processing Applications and Technology (ICSPAT) | en_US |
| dc.citation.location | Dallas, TX | en_US |
| dc.contributor.author | Rajagopal, Sridhar | en_US |
| dc.contributor.author | Jones, Bryan Allen | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:59:04Z | en_US |
| dc.date.available | 2007-10-31T00:59:04Z | en_US |
| dc.date.issued | 2000-10-20 | en_US |
| dc.date.modified | 2003-11-10 | en_US |
| dc.date.note | 2001-08-30 | en_US |
| dc.date.submitted | 2000-10-20 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | This paper presents a multiprocessor solution to meet real-time requirements of implementing advanced algorithms for multiuser channel estimation and detection for third and fourth generation wireless base-station receivers. We identify the key bottlenecks in the algorithms and task-partition the algorithms on multiple processors. We get speedups, ranging from 1.19X to 5.92X for a dual-DSP implementation due to both additional computational power and additional internal memory compared to a single DSP implementation using external memory. We also identify parts of the algorithm that exhibit bit-level parallelism, not utilized by DSPs. FPGAs can then be used to accelerate these parts and meet real-time requirements of 128 Kbps for next generation wireless systems. | en_US |
| dc.description.sponsorship | Texas Advanced Technology Program | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | S. Rajagopal, B. A. Jones and J. R. Cavallaro, "Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," 2000. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20223 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | multiprocessor | en_US |
| dc.subject | DSPs | en_US |
| dc.subject | FPGAs | en_US |
| dc.subject | receiver algorithms | en_US |
| dc.subject | task partitioning | en_US |
| dc.subject.keyword | multiprocessor | en_US |
| dc.subject.keyword | DSPs | en_US |
| dc.subject.keyword | FPGAs | en_US |
| dc.subject.keyword | receiver algorithms | en_US |
| dc.subject.keyword | task partitioning | en_US |
| dc.title | Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
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