A programmable baseband processor design for software defined radios
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | IEEE Midwest Conference on Circuits and Systems | en_US |
| dc.citation.firstpage | 413 | |
| dc.citation.lastpage | 416 | |
| dc.citation.location | Tulsa, OK | en_US |
| dc.citation.volumeNumber | 3 | en |
| dc.contributor.author | Rajagopal, Sridhar | en_US |
| dc.contributor.author | Rixner, Scott | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:59:33Z | |
| dc.date.available | 2007-10-31T00:59:33Z | |
| dc.date.issued | 2002-08-20 | en |
| dc.date.modified | 2003-11-09 | en_US |
| dc.date.note | 2002-08-12 | en_US |
| dc.date.submitted | 2002-08-20 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | Future wireless systems need extremely fast and flexible architectures to support varying standards, algorithms and protocols with data rates in the range of 10-100 Mbps. Software Defined Radios (SDRs) based on DSP-FPGAs are a widely proposed solution for these systems. However, these SDR solutions have not been able to meet real-time requirements. We propose a programmable architecture solution for SDRs using a stream-based architecture based on the <i>Imagine</i> media processor. The configurable <i>Imagine</i> simulator allows us to investigate issues such as memory bottlenecks, number and type of functional units needed, and the utilization of those functional units. To evaluate stream-based architectures for baseband processing, we parallelize and implement sophisticated baseband algorithms including multiuser estimation, multiuser detection and Viterbi decoding on this simulator. We present the bottlenecks in such a stream-based architecture for efficient communications processing. Comparisons with current generation DSP-based solutions show orders-of-magnitude performance improvements, both due to the stream-based nature of computations as well as the increase in the number of functional units having a high utilization factor. The result is a baseband processor designed with broad system functionality and flexibility that approaches real-time performance for future wireless systems. | en_US |
| dc.description.sponsorship | Texas Advanced Technology Program | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | S. Rajagopal, S. Rixner and J. R. Cavallaro, "A programmable baseband processor design for software defined radios," vol. 3, 2002. | |
| dc.identifier.doi | http://dx.doi.org/10.1109/MWSCAS.2002.1187061 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20233 | |
| dc.language.iso | eng | |
| dc.publisher | IEEE | en_US |
| dc.subject | communications processor | * |
| dc.subject | multiuser estimation | * |
| dc.subject | multiuser detection | * |
| dc.subject | Viterbi decoding | * |
| dc.subject.keyword | communications processor | en_US |
| dc.subject.keyword | multiuser estimation | en_US |
| dc.subject.keyword | multiuser detection | en_US |
| dc.subject.keyword | Viterbi decoding | en_US |
| dc.title | A programmable baseband processor design for software defined radios | en_US |
| dc.type | Conference paper | |
| dc.type.dcmi | Text |