Validation of Rice Parallel Processing Testbed applications
| dc.contributor.advisor | Jump, J. Robert | |
| dc.creator | Covington, Richard Glenn | |
| dc.date.accessioned | 2009-06-04T00:05:10Z | |
| dc.date.available | 2009-06-04T00:05:10Z | |
| dc.date.issued | 1989 | |
| dc.description.abstract | The Rice Parallel Processing Testbed (RPPT) is a collection of software tools for simulating the interaction of parallel programs and parallel architectures. The testbed uses a novel technique called execution-driven simulation, whereby the pseudo-concurrent execution of a parallel algorithm, augmented by profiling code, is used to drive the discrete-event simulation of a parallel architecture. This technique is intermediate between the high accuracy and low computational efficiency of instruction-level simulations and the less accurate but high efficiency statistical distribution-driven simulations, effectively combining attractive features of both of these techniques. The technique provides estimates of overall execution time, as well as more detailed performance indices such as communication vs. computation time, message passing traffic, and processor utilization. The methodology and implementation of the testbed are discussed at length and are compared with recently published related projects. The implementation has been a collective effort involving several people, and the author's contribution to the effort is outlined. Testbed predictions are given for a set of parallel numerical algorithms--LU decomposition, eigenvalue-eigenvector determination, FFT--simulated for a hypercube, and the predictions are validated against measurement of actual program execution on an Intel iPSC 16-node hypercube. | |
| dc.format.extent | 209 p. | en_US |
| dc.format.mimetype | application/pdf | |
| dc.identifier.callno | Thesis E.E. 1989 Covington | |
| dc.identifier.citation | Covington, Richard Glenn. "Validation of Rice Parallel Processing Testbed applications." (1989) Diss., Rice University. <a href="https://hdl.handle.net/1911/16221">https://hdl.handle.net/1911/16221</a>. | |
| dc.identifier.uri | https://hdl.handle.net/1911/16221 | |
| dc.language.iso | eng | |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | |
| dc.subject | Computer science | |
| dc.title | Validation of Rice Parallel Processing Testbed applications | |
| dc.type | Thesis | |
| dc.type.material | Text | |
| thesis.degree.department | Electrical Engineering | |
| thesis.degree.discipline | Engineering | |
| thesis.degree.grantor | Rice University | |
| thesis.degree.level | Doctoral | |
| thesis.degree.name | Doctor of Philosophy |
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