CMOS Processor Element For A Fault-Tolerant SVD Array
| dc.citation.bibtexName | article | en_US |
| dc.citation.firstpage | 483 | |
| dc.citation.journalTitle | Conference on Advanced Signal Processing Algorightms, Architectures, and Implementations | en_US |
| dc.citation.lastpage | 496 | |
| dc.citation.location | San Diego, CA | en_US |
| dc.citation.volumeNumber | 2027 | en_US |
| dc.contributor.author | Kota, Kishore | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:50:39Z | |
| dc.date.available | 2007-10-31T00:50:39Z | |
| dc.date.issued | 1993-07-20 | |
| dc.date.modified | 2001-08-30 | en_US |
| dc.date.submitted | 2001-08-30 | en_US |
| dc.description | Journal Paper | en_US |
| dc.description.abstract | This paper describes the VLSI implementation of a CORDIC based processor element for use in a fault-reconfigurable systolic array to compute the Singular Value Decomposition (SVD) of a matrix. The chip implements a time redundant fault tolerance scheme, which allows processors adjacent to a faulty processor to act as computation backup during the systolic idle time. Also, processors around a fault collaborate to reroute data around the faulty processor. This form of time redundancy is attractive when tolerance to a few faults needs to be achieved with little hardware overhead. Many of the proposed systolic array architectures for SVD are made of slightly dissimilar processors. We show that a physically uniform stucture of the array simplifies the design, especially for fault-reconfigurable processor arrays. Our implementation required the addition of a number of architectural features to ease custom VLSI design. We eliminated the special pyhysical edge connections proposed by earlier mesh architectures by adding extra programmablility to the chip and embedding the original array in a regular toroidal structure. This allows undersized problems to be mapped onto the same physical array without padding the matrix with rows or colums of zeros. In addition, an entire row or column may be bypassed without the need for external switches, thus providing an extra degree of fault tolerance. The chip was designed in a CMOS double-metal 2ì process and is 8954u x 7840ì. The overheads incurred in adding the time redundancy were an increase of about 40% in the number of controller states and a backup set of register to store the faulty neighbor's data. The array was initially simulated at t highter level using VHDL descriptions and schematic capture software. This was then mapped to a custon chip using rapid-prototyping techniques. | en_US |
| dc.identifier.citation | K. Kota and J. R. Cavallaro, "CMOS Processor Element For A Fault-Tolerant SVD Array," <i>Conference on Advanced Signal Processing Algorightms, Architectures, and Implementations,</i> vol. 2027, 1993. | |
| dc.identifier.doi | http://dx.doi.org/10.1117/12.160459 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20038 | |
| dc.language.iso | eng | |
| dc.subject | Singular Value Decomposition (SVD) array | * |
| dc.subject | CMOS Processor | * |
| dc.subject.keyword | Singular Value Decomposition (SVD) array | en_US |
| dc.subject.keyword | CMOS Processor | en_US |
| dc.title | CMOS Processor Element For A Fault-Tolerant SVD Array | en_US |
| dc.type | Journal article | |
| dc.type.dcmi | Text |
Files
Original bundle
1 - 1 of 1