An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
| dc.citation.firstpage | 1 | |
| dc.citation.issueNumber | Article ID 57134 | en_US |
| dc.citation.journalTitle | EURASIP Journal on Applied Signal Processing | en_US |
| dc.citation.lastpage | 18 | |
| dc.citation.volumeNumber | 2006 | en_US |
| dc.contributor.author | Guo, Yuanbin | |
| dc.contributor.author | Zhang, Jianzhong | |
| dc.contributor.author | McCain, Dennis | |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-04T21:07:58Z | |
| dc.date.available | 2012-06-04T21:07:58Z | |
| dc.date.issued | 2006-02-01 | eng |
| dc.description.abstract | We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size (NF×NF) with O((NF)3) complexity to some FFT operations with O(NF log2(F)) complexity and the inverse of some (N×N) submatrices.We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4×4) high-order receiver from partitioned (2 × 2) submatrices. This leads to more parallel VLSI design with 3× further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology. | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | Y. Guo, J. Zhang, D. McCain and J. R. Cavallaro, "An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture," <i>EURASIP Journal on Applied Signal Processing,</i> vol. 2006, no. Article ID 57134, 2006. | * |
| dc.identifier.doi | http://dx.doi.org/10.1155/ASP/2006/57134 | en_US |
| dc.identifier.issn | 10.1155/ASP/2006/57134 | |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=9475738772029113561&hl=en&as_sdt=0,44 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64215 | |
| dc.language.iso | eng | en |
| dc.publisher | Hindawi Publishing Corporation | en_US |
| dc.subject | MIMO | en_US |
| dc.subject | CDMA downlink | en_US |
| dc.subject | Optimization | en_US |
| dc.subject | VLSI | en_US |
| dc.title | An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture | en_US |
| dc.type | Journal article | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |